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([2a01:e0a:106d:1080:cbfe:649:7f17:8b95]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485276b75eesm22233595e9.14.2026.03.06.02.38.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Mar 2026 02:38:15 -0800 (PST) Message-ID: <483d3eea-d1aa-447e-b703-2bdeb3cf0e80@linaro.org> Date: Fri, 6 Mar 2026 11:38:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v2] phy: rockchip: naneng-combphy: Consolidate SSC configuration To: Shawn Lin , Vinod Koul Cc: linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org, Heiko Stuebner , linux-kernel@vger.kernel.org References: <1772696450-139583-1-git-send-email-shawn.lin@rock-chips.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <1772696450-139583-1-git-send-email-shawn.lin@rock-chips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/5/26 08:40, Shawn Lin wrote: > The PCIe SSC configuration for the RK3588 and RK3576 SoCs required > additional tuning which is missing. When adding these same SSC > configurations for both of these two SoCs, as well as upcoming > platforms, it's obvious the SSC setup code was largely duplicated > across the platform-specific configuration functions. This becomes > harder to maintain as more platforms are added. > > So extract the common SSC logic into a shared helper function, > rk_combphy_common_cfg_ssc(). This cleans up the per-platform drivers > and centralizes the standard configuration as possible. > > Signed-off-by: Shawn Lin > > --- > > Changes in v2: > - rework to consolidate more configuration > - reword the commit message > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 173 +++++++++------------ > 1 file changed, 73 insertions(+), 100 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > index b60d6bf..2b0f152 100644 > --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > @@ -121,6 +121,7 @@ > #define RK3568_PHYREG32_SSC_OFFSET_500PPM 1 > > #define RK3568_PHYREG33 0x80 > +#define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5) > #define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) > #define RK3568_PHYREG33_PLL_KVCO_SHIFT 2 > #define RK3568_PHYREG33_PLL_KVCO_VALUE 2 > @@ -446,6 +447,74 @@ static int rockchip_combphy_probe(struct platform_device *pdev) > return PTR_ERR_OR_ZERO(phy_provider); > } > > +static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsigned long rate) > +{ > + struct device_node *np = priv->dev->of_node; > + u32 val; > + > + if (!priv->enable_ssc) > + return; > + > + /* Set SSC downward spread spectrum for PCIe and USB3 */ > + if (priv->type == PHY_TYPE_PCIE || priv->type == PHY_TYPE_USB3) { > + val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); > + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > + } > + > + /* Set SSC downward spread spectrum +500ppm for SATA in 100MHz */ > + if (priv->type == PHY_TYPE_SATA && rate == REF_CLOCK_100MHz) { > + val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK, > + RK3568_PHYREG32_SSC_DOWNWARD); > + val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK, > + RK3568_PHYREG32_SSC_OFFSET_500PPM); > + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, > + RK3568_PHYREG32); > + } > + > + /* Enable SSC */ > + val = readl(priv->mmio + RK3568_PHYREG8); > + val |= RK3568_PHYREG8_SSC_EN; > + writel(val, priv->mmio + RK3568_PHYREG8); > + > + /* Some SoCs need tuning PCIe SSC instead of default configuration in 24MHz */ > + if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") && > + !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy")) > + return; > + > + /* PLL control SSC module period should be set if need tuning */ > + val = readl(priv->mmio + RK3568_PHYREG33); > + val |= RK3568_PHYREG33_PLL_SSC_CTRL; > + writel(val, priv->mmio + RK3568_PHYREG33); > + > + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { > + /* Set PLL loop divider */ > + writel(0x00, priv->mmio + RK3576_PHYREG17); > + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); > + > + /* Set up rx_pck invert and rx msb to disable */ > + writel(0x00, priv->mmio + RK3588_PHYREG27); > + > + /* > + * Set up SU adjust signal: > + * su_trim[7:0], PLL KVCO adjust bits[2:0] to min > + * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101 > + * su_trim[23:16], CKRCV adjust > + * su_trim[31:24], CKDRV adjust > + */ > + writel(0x90, priv->mmio + RK3568_PHYREG11); > + writel(0x02, priv->mmio + RK3568_PHYREG12); > + writel(0x08, priv->mmio + RK3568_PHYREG13); > + writel(0x57, priv->mmio + RK3568_PHYREG14); > + writel(0x40, priv->mmio + RK3568_PHYREG15); > + > + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); > + > + val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, > + RK3576_PHYREG33_PLL_KVCO_VALUE); > + writel(val, priv->mmio + RK3568_PHYREG33); > + } > +} > + > static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) > { > const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; > @@ -600,21 +669,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) > > switch (priv->type) { > case PHY_TYPE_PCIE: > - /* Set SSC downward spread spectrum */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > - > rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); > break; > case PHY_TYPE_USB3: > - /* Set SSC downward spread spectrum */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, > - RK3568_PHYREG32); > - > /* Enable adaptive CTLE for USB3.0 Rx */ > rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN, > RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15); > @@ -706,11 +766,7 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) > } > } > > - if (priv->enable_ssc) { > - val = readl(priv->mmio + RK3568_PHYREG8); > - val |= RK3568_PHYREG8_SSC_EN; > - writel(val, priv->mmio + RK3568_PHYREG8); > - } > + rk_combphy_common_cfg_ssc(priv, rate); > > return 0; > } > @@ -755,11 +811,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > > switch (priv->type) { > case PHY_TYPE_PCIE: > - /* Set SSC downward spread spectrum. */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; > - > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > - > rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); > @@ -767,10 +818,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > break; > > case PHY_TYPE_USB3: > - /* Set SSC downward spread spectrum. */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT, > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > - > /* Enable adaptive CTLE for USB3.0 Rx. */ > val = readl(priv->mmio + RK3568_PHYREG15); > val |= RK3568_PHYREG15_CTLE_EN; > @@ -880,13 +927,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > > writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); > writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); > - } else if (priv->type == PHY_TYPE_SATA) { > - /* downward spread spectrum +500ppm */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; > - val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << > - RK3568_PHYREG32_SSC_OFFSET_SHIFT; > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, > - RK3568_PHYREG32); > } > break; > > @@ -909,11 +949,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > } > } > > - if (priv->enable_ssc) { > - val = readl(priv->mmio + RK3568_PHYREG8); > - val |= RK3568_PHYREG8_SSC_EN; > - writel(val, priv->mmio + RK3568_PHYREG8); > - } > + rk_combphy_common_cfg_ssc(priv, rate); > > return 0; > } > @@ -972,10 +1008,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) > > switch (priv->type) { > case PHY_TYPE_PCIE: > - /* Set SSC downward spread spectrum */ > - val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > - > rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); > rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); > @@ -983,10 +1015,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) > break; > > case PHY_TYPE_USB3: > - /* Set SSC downward spread spectrum */ > - val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > - > /* Enable adaptive CTLE for USB3.0 Rx */ > val = readl(priv->mmio + RK3568_PHYREG15); > val |= RK3568_PHYREG15_CTLE_EN; > @@ -1110,14 +1138,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) > writel(0x88, priv->mmio + RK3568_PHYREG13); > writel(0x56, priv->mmio + RK3568_PHYREG14); > } else if (priv->type == PHY_TYPE_SATA) { > - /* downward spread spectrum +500ppm */ > - val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK, > - RK3568_PHYREG32_SSC_DOWNWARD); > - val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK, > - RK3568_PHYREG32_SSC_OFFSET_500PPM); > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, > - RK3568_PHYREG32); > - > /* ssc ppm adjust to 3500ppm */ > rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK, > RK3576_PHYREG10_SSC_PCM_3500PPM, > @@ -1156,39 +1176,7 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) > } > } > > - if (priv->enable_ssc) { > - val = readl(priv->mmio + RK3568_PHYREG8); > - val |= RK3568_PHYREG8_SSC_EN; > - writel(val, priv->mmio + RK3568_PHYREG8); > - > - if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { > - /* Set PLL loop divider */ > - writel(0x00, priv->mmio + RK3576_PHYREG17); > - writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); > - > - /* Set up rx_pck invert and rx msb to disable */ > - writel(0x00, priv->mmio + RK3588_PHYREG27); > - > - /* > - * Set up SU adjust signal: > - * su_trim[7:0], PLL KVCO adjust bits[2:0] to min > - * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101 > - * su_trim[23:16], CKRCV adjust > - * su_trim[31:24], CKDRV adjust > - */ > - writel(0x90, priv->mmio + RK3568_PHYREG11); > - writel(0x02, priv->mmio + RK3568_PHYREG12); > - writel(0x08, priv->mmio + RK3568_PHYREG13); > - writel(0x57, priv->mmio + RK3568_PHYREG14); > - writel(0x40, priv->mmio + RK3568_PHYREG15); > - > - writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); > - > - val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, > - RK3576_PHYREG33_PLL_KVCO_VALUE); > - writel(val, priv->mmio + RK3568_PHYREG33); > - } > - } > + rk_combphy_common_cfg_ssc(priv, rate); > > return 0; > } > @@ -1255,10 +1243,6 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) > } > break; > case PHY_TYPE_USB3: > - /* Set SSC downward spread spectrum */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); > - > /* Enable adaptive CTLE for USB3.0 Rx. */ > val = readl(priv->mmio + RK3568_PHYREG15); > val |= RK3568_PHYREG15_CTLE_EN; > @@ -1343,13 +1327,6 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) > > /* Set up su_trim: */ > writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); > - } else if (priv->type == PHY_TYPE_SATA) { > - /* downward spread spectrum +500ppm */ > - val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; > - val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << > - RK3568_PHYREG32_SSC_OFFSET_SHIFT; > - rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, > - RK3568_PHYREG32); > } > break; > default: > @@ -1371,11 +1348,7 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) > } > } > > - if (priv->enable_ssc) { > - val = readl(priv->mmio + RK3568_PHYREG8); > - val |= RK3568_PHYREG8_SSC_EN; > - writel(val, priv->mmio + RK3568_PHYREG8); > - } > + rk_combphy_common_cfg_ssc(priv, rate); > > return 0; > } Reviewed-by: Neil Armstrong Thanks, Neil