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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-62fadb1ee79sm12382698a12.33.2025.09.24.05.31.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Sep 2025 05:31:21 -0700 (PDT) Message-ID: <483e0f79-1725-435b-830c-9c1dba886186@oss.qualcomm.com> Date: Wed, 24 Sep 2025 14:31:19 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Glymur compatible To: Wesley Cheng , Dmitry Baryshkov Cc: krzk+dt@kernel.org, conor+dt@kernel.org, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org References: <20250920032108.242643-1-wesley.cheng@oss.qualcomm.com> <20250920032108.242643-2-wesley.cheng@oss.qualcomm.com> <588fd98b-ed22-2940-a749-d4601f77b0b1@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <588fd98b-ed22-2940-a749-d4601f77b0b1@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=KNxaDEFo c=1 sm=1 tr=0 ts=68d3e49b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=DIBu_eTfnsobS-0nAiIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: hXH1hC9TQUBE6lzBmoesNeIN3MSk6RsI X-Proofpoint-ORIG-GUID: hXH1hC9TQUBE6lzBmoesNeIN3MSk6RsI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIzMDEzOCBTYWx0ZWRfX5UGwlurv4ozB auo46b+Zaqsf/AvVjNRL4QDUFleW67bHpGxejpzZaIaoqwGCr1bUTay/vNB9j0qGKveW2b9b2F3 /VvNoNOo75Yo72qL/7ZmZ1gbICPJUP0mC9gY5jfxaeMabb0wLfqVypQrzvO/ABOc9D6SDOilN0g pPSMWzqR1lrFKvOXwQErA6zQCwvviO5dp2DRbTUeIPY1ThHCPQR3f5OPl/S/5q8bpMJM6xo1Uog q2WhM8n4QZ9EM7VyWMQJHsTHcGs8nE6IC0EcIpIWCXKc2MVLjZL5W061q8usJDUOo84izEKK28Z SUGqyjiy4PPzyGLf9t57O3tBpZkGZJALK+//+ywFpCqZ7NVzz45Jm6EBECqcVe7CWsfT9ohjQGd /ZP8U1Iu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_03,2025-09-22_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509230138 On 9/22/25 10:52 PM, Wesley Cheng wrote: > > > On 9/20/2025 8:18 AM, Dmitry Baryshkov wrote: >> On Fri, Sep 19, 2025 at 08:21:00PM -0700, Wesley Cheng wrote: >>> Define a Glymur compatible string for the QMP PHY combo driver, along with >>> resource requirements.  Add a different identifier for the primary QMP PHY >>> instance as it does not require a clkref entry. >> >> Are register programming the same for both of them or not? If it's the >> same, it might be not necessary to have different compatibles. >> > > Hi Dmitry, > > Yes, the register programming sequences are the same, but the number of clocks are different between the primary and the other controllers. Specifically, on the primary USB controller, we don't have a clkref in the TCSR.  Was just adding a separate compatible ID to define the max clock items.  However, I do see that even if I only need 4 clks (for the primary) it technically doesn't break the DT bindings definition, as minItems = 4 and maxItems = 5 for the clock and clock-names fields. We can just stick &xo_board in there and avoid the mess XO physically supplies the PHY even if it's not programmatically configurable like other gate/branch clocks Konrad