From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756702AbdAKTTK (ORCPT ); Wed, 11 Jan 2017 14:19:10 -0500 Received: from mail-sn1nam01on0083.outbound.protection.outlook.com ([104.47.32.83]:11380 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932189AbdAKTTI (ORCPT ); Wed, 11 Jan 2017 14:19:08 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=David.Daney@cavium.com; Subject: Re: [PATCH] PCI: thunder-pem: Add support for cn81xx and cn83xx SoCs. To: David Daney , , , Bjorn Helgaas , References: <20170111191141.28747-1-ddaney.cavm@gmail.com> From: David Daney Message-ID: <4841267a-35d8-4065-edb6-d0d4b1f272ed@caviumnetworks.com> Date: Wed, 11 Jan 2017 11:19:00 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <20170111191141.28747-1-ddaney.cavm@gmail.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [50.233.148.156] X-ClientProxiedBy: BLUPR07CA065.namprd07.prod.outlook.com (10.160.24.20) To CY1PR07MB2133.namprd07.prod.outlook.com (10.164.112.11) X-MS-Office365-Filtering-Correlation-Id: c44c33e5-c231-4de8-7a2e-08d43a56b58f X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:CY1PR07MB2133; X-Microsoft-Exchange-Diagnostics: 1;CY1PR07MB2133;3:MasBByZiivWdpFvlNmg4hiIQRG9neLRcVWgd0Kb+Oi8t/BLd/ag/4DtRfVPUvLcbbne2zDyK8iZrj6mwdG7Y4SPnlZVuc39TdncjxwJKJMSW5ZPxJQ+NK7W0c/9QmJMUheoDY6m8+UiMhRfZugrrQiflJ09DGIc6/L9REW1GQ3z/aNMKiu1UW1TTSXcsD8zA38O3GtZPI5gztXqqRHrMJjtgqTcoE2f4bVruu74mvO2UrznY3ooa3EZsCnVXqgfmN/SoJk282UxfT0awAo3kAA==;25:bMMGn3gkslyoqdpDkOQooqluI2QSH/GyHC1FOTKoPE+jIxiZa49pBsZwIyUZ0kpCqBOUT9nT4JRnZH1CXeM6i7N3JJzS0VvCaRjO2I++kwlFRuwDTQOzdxoLvoHsMgr6CggxWCdq5CE6IfXKh9G8XggSFLitKMKdGH21viXR3phogWGurERJbB154BF/YFRWtIt4F2eGImOCRNlyqE16ocROCeo1HZ4YV8cR1t2ErS3xqqYBy8MPSyxtt+bcB0AR+nJOmKYe6NID8EDpFoAuvG3awtzeEhg2oZwXHUM5XkgiLOJCWAJUI0qm9OIlnQzmCGCFQBeCyxkTl+m1yfdQ4B/hWoQjvjVr8fMVIefdxwEJYCLdYeVu6D9j7MmFe1oBQSgE9gHeBh+ZIxtIjcFRkzV5TGH4ddlmDLDFc0AetyhDmRlW69OBvyu78pO7mlIj5EaKU9erxUBAvgAK7+mCLQ== X-Microsoft-Exchange-Diagnostics: 1;CY1PR07MB2133;31:siW4jnOysx2aebWKRx4wZV9OBem8H289BBEyMedlAI7B+lrQDd8byCM9h7aWNe+UWljLod9c2aqIdujAOowJCuCH8jYKTPIcXsR+6gZRHKf1IxTWzGtemv0efjhtNE2WptNK4v8k2NUPDWmR4Mlr9zMC/2Joj8E12gi3tPle1HgLiM2WMFUU2zzCO0JhmY/zVcxO9gQhlvn/l+WSLEvRuqI8JvZsD6p9PDl03JmOd8bjR9kA5sOtd042kD5Ppe0vqmRhe5SyQC3zJXdGU6IwUuqwk2fAkYBTUeEmVRTEKnA=;20:bvEX1zwBR9K1jxxTSDu8jodvEpkykxxttH/LJ7N0S41/SHLeDhdAO1c7rinPIX/zQgtPNOnRumiBgBKJaqS+irJLb1375+9351ecnqk2/kG6duy/qgPOm+r+XE7FglulHbkjIzixlN95ctoktMFdXNrq182QdnRe+iGANb+zwzrHvfpvGEWdB188fUnos3Q8ZdCaQp1aQzNrgrd99vsid1XPsDaHIgmkHLxKuzrBQfQAmlKsKw5AlDbti2E9vDtFonzsZaumcJujyM24qMiznHjBUCN4P71dc9UDALjts1ziqckV+60UHL6vQ3JGLz6Svl0WJE5uO6EmXTV4XxDT/3zjvUoIvQ+QYsELOLEKsdEVKe/g7IundFt/uWy4W08ihesMX5yJUIqWF5YWwa/cuglyo1r6IcVsp6/cg5ckucGu0uYf92ZlnRi5+oLsrZTyl0zDB4ycB3N24UGq41wUXgSVgl14DcHh7RpQFXFFuhCUwTAtMYB6EMNYyAKmltUreJIlAzkvuhb6LJDiDby2TJC7uz3//A8CtG0rQM+cqFcr1vI9EmMH8a3X8YAwJMaY0Rcu0qWR17WBRTqKWZ1xLTlfpxw/35LgH7/NcQLP7ws= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; 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> + u64 read_val, tmp_val; > struct pci_config_window *cfg = bus->sysdata; > struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; > > @@ -65,13 +65,28 @@ static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn, > read_val |= 0x00007000; /* Skip MSI CAP */ > break; > case 0x70: /* Express Cap */ > - /* PME interrupt on vector 2*/ > - read_val |= (2u << 25); > + /* > + * Change PME interrupt to vector 2 on T88 where it > + * reads as 0, else leave it alone. > + */ > + if (!(read_val & (0x1f << 25))) > + read_val |= (2u << 25); > break; > case 0xb0: /* MSI-X Cap */ > - /* TableSize=4, Next Cap is EA */ > + /* TableSize=2 or 4, Next Cap is EA */ > read_val &= 0xc00000ff; > - read_val |= 0x0003bc00; > + /* > + * If Express Cap(0x70) raw PME vector reads as 2 we are on Crap! The comment is incorrect s/2/0/, I guess I will send a corrected patch. The code is correct though. > + * T88 and TableSize is reported as 4, else TableSize > + * is 2. > + */ > + writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD); > + tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); > + tmp_val >>= 32; > + if (!(tmp_val & (0x1f << 25))) > + read_val |= 0x0003bc00; > + else > + read_val |= 0x0001bc00; > break; > case 0xb4: > /* Table offset=0, BIR=0 */ >