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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0a396fsm1103435066b.42.2025.08.06.05.35.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Aug 2025 05:35:29 -0700 (PDT) Message-ID: <48478a05-59b9-4f2e-9339-255e513a9cb2@oss.qualcomm.com> Date: Wed, 6 Aug 2025 14:35:26 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller To: Varadarajan Narayanan , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, djakov@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Cc: Sricharan Ramabadhran , Md Sadre Alam References: <20250806112807.2726890-1-quic_varada@quicinc.com> <20250806112807.2726890-3-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250806112807.2726890-3-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Mftsu4/f c=1 sm=1 tr=0 ts=68934c16 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=nqClpMi1XL7t9EIYa0wA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: qoLNr6YPFHmR3cfqVZ1oiqbeaZPe_kjM X-Proofpoint-GUID: qoLNr6YPFHmR3cfqVZ1oiqbeaZPe_kjM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDAwOSBTYWx0ZWRfX0VpgUgBf9V+b mVbDiwvZ9XZnVoNUl63lOb73iPjroJ7BKXnc9qnnIMN4JS+reKbAQOJET1Ckvjizm3O7963wpho GK/YTt3qrdE5j5ZJ1ae0GlkeEyp9CUbqxAAz3KmssBWZoGyt0yni3V/nFO77gl0aBHv600J4Int M1iCeqQb3S/36serBBfTG5u4TztDyxumvxIJoKJ8j91wHth/PWVJhZ8cRgGMTAMjkXkAry0zd32 kj72sU1sn4ryY5Cc9ukJoudYtisy92eDmyEPL4ZbdG2NzZB6gleOiDVdWqaPFRJHMPOlF1LKEcP a7LV7r6nvZh08z8mq97LDEUGT9GT38FD9PssEE2zasosq+7DfWhcDb3HTeg06SWvVt1H39cLzAs pK8gpXLi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-06_03,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060009 On 8/6/25 1:28 PM, Varadarajan Narayanan wrote: > From: Sricharan Ramabadhran > > CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. > Add support for the APSS PLL, RCG and clock enable for ipq5424. > The PLL, RCG register space are clubbed. Hence adding new APSS driver > for both PLL and RCG/CBC control. Also the L3 cache has a separate pll > and needs to be scaled along with the CPU and is modeled as an ICC clock. > > Co-developed-by: Md Sadre Alam > Signed-off-by: Md Sadre Alam > Signed-off-by: Sricharan Ramabadhran > [ Removed clock notifier, moved L3 pll to icc-clk, used existing > alpha pll structure ] > Signed-off-by: Varadarajan Narayanan > --- [...] > +static struct clk_branch apss_silver_core_clk = { > + .halt_reg = 0x008c, > + .clkr = { > + .enable_reg = 0x008c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data) { > + .name = "apss_silver_core_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &apss_silver_clk_src.clkr.hw }, Odd closing bracket placement [...] > +static const struct clk_parent_data parents_l3_clk_src[] = { > + { .fw_name = "xo-board-clk" }, > + { .fw_name = "clk_ref" }, > + { .hw = &ipq5424_l3_pll.clkr.hw }, > +}; One more remnant /\ Konrad