Re: [RFC PATCH v2 00/12] spi: cadence-quadspi: add PHY tuning support

[Santhosh Kumar K <s-k6@ti.com>]

On 13/02/26 14:31, Miquel Raynal wrote:
> On 07/02/2026 at 00:58:03 +0530, Santhosh Kumar K <s-k6@ti.com> wrote:
> 
>> On 05/02/26 21:18, Miquel Raynal wrote:
>>> Hi Santhosh,
>>>
>>>> I am surprised by these numbers, I would expect these to get higher for
>>>> SPI NANDs. I will test the series and report my observations, especially
>>>> since there is also ODDR SPI NAND support now (in nand/next, should be
>>>> part of my upcoming merge request to Linus for 6.19+1);
>>> I just tested the series, here are some numbers I grabbed on TI AM62A7
>>> LP SK with a Winbond W35N02 SPI NAND chip (so in the end very close to
>>> your report):
>>>    +-----------------+-----------+------------+
>>>    | SPI NAND        | no tuning | PHY tuning |
>>>    | Unit: MiB/s     |   25MHz   |   166MHz   |
>>>    |-----------------+-----------+------------|
>>>    | Octal SDR read  |   13.8    |    34.2    |
>>>    |           write |    7.2    |    10.2    |
>>>    |-----------------+-----------+------------|
>>>    | Octal DTR read  |   21.2    |     N/A    |
>>>    |           write |    9.0    |     N/A    |
>>>    +-----------------+-----------+------------+
>>> Please mind I used MiB/s and not MB/s (so kiB / 1024), I don't know
>>> which one you used for measuring, as you marked MB, whereas the most
>>> common unit seems to be MiB.
>>> However PHY tuning failed in Octal DTR mode (your series applied on
>>> top
>>> of nand/next) with the following logs, can you have a look?
>>> [    2.261647] spi-nand spi0.0: Winbond SPI NAND was found.
>>> [    2.266956] spi-nand spi0.0: 128 MiB, block size: 256 KiB, page size: 4096, OOB size: 128
>>> [    2.285257] cadence-qspi fc40000.spi: PHY tuning failed: -2
>>> [    2.290835] spi-nand spi0.0: Failed to execute PHY tuning: -2
>>
>> Unfortunately, due to a known erratum in the Cadence controller, PHY DDR
>> mode cannot be used with 2-byte addressing.
>>
>> Refer:
>> Errata i2383: OSPI: 2-byte address is not supported in PHY DDR mode [1]
>>
>> As a result, the Cadence controller supports only the following
>> operating modes:
>>   - PHY DDR mode with 4-byte addressing
>>   - PHY SDR mode
>>   - TAP (non-PHY) DDR mode
>>   - TAP (non-PHY) SDR mode
> 
> I do not think we have 4-byte addressing capabilities on SPI NAND chips,
> esp. Winbond's chips. So there is a down side: the core will pick-up
> Octal DTR modes rather than Octal SDR (with PHY) mode, which is not the
> fastest mode. Maybe we can guess that once we have access to the max
> (tuned PHY) spi frequency, with an extra flag in the driver indicating
> that the PHY speed is not accessible in DTR mode. But this again
> requires different handling between SPI NAND and SPI NOR, as SPI NOR
> IIRC may have 4-byte addressing capabilities.

I'm currently handling this in the Cadence controller's supports_op()
callback, and it seems to be working as expected.

If a DDR operation is passed with addr.nbytes <= 2 and PHY tuning
support is available, return false. I'll include this change in v3.

Regards,
Santhosh.

> 
> Thanks,
> Miquèl