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The same value was later carried > over unchanged when the ICE node was split out from the UFS node into > its own DT entry. > > Correct the register size to match the hardware specification. > > Fixes: 276ee34a40c1 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock") > Signed-off-by: Kuldeep Singh > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 920a2d1c04d0..3984d6f8932d 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -5373,7 +5373,7 @@ ufs_mem_phy: phy@1d87000 { > ice: crypto@1d88000 { > compatible = "qcom,sm8450-inline-crypto-engine", > "qcom,inline-crypto-engine"; > - reg = <0 0x01d88000 0 0x8000>; > + reg = <0 0x01d88000 0 0x18000>; > clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > }; > > Reviewed-by: Harshal Dev Regards, Harshal