From: Elad Lahav <elad_lahav@users.sourceforge.net>
To: David Miller <davem@davemloft.net>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] Initial support for Niagara T1 performance counters
Date: Thu, 11 Sep 2008 19:34:46 -0400 [thread overview]
Message-ID: <48C9AB16.3060706@users.sourceforge.net> (raw)
In-Reply-To: <20080911.145937.178601244.davem@davemloft.net>
David Miller wrote:
> Full support for both T1 and T2 performance counters (as well as those
> of all other sparc64 processors) is contained in the perfmon2 tree.
Fair enough, I wasn't aware that perfmon supported the T1.
Just for the record, is the implementation correct? Specifically, is
this the right way to extract the PIL at the time of the trap?
Thanks,
Elad
next prev parent reply other threads:[~2008-09-11 23:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-11 21:05 Elad Lahav
2008-09-11 21:59 ` David Miller
2008-09-11 23:34 ` Elad Lahav [this message]
2008-09-11 23:47 ` David Miller
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