From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DBF7C74A5B for ; Thu, 30 Mar 2023 03:04:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbjC3DEf (ORCPT ); Wed, 29 Mar 2023 23:04:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229504AbjC3DEa (ORCPT ); Wed, 29 Mar 2023 23:04:30 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A6395240; Wed, 29 Mar 2023 20:04:29 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32U34NOL049681; Wed, 29 Mar 2023 22:04:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680145463; bh=rwgY+brqpxleHmcpDlVKMBclpHE9SNEizgk3yrgzpDo=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=QX6V0Cs+IC/t67bt0ySHYpoyuLEqHOM9duE1iM9Zk3Y3Uc+cpla4T9m615pQmfAN9 2DunSTNclIXIBbUJbvvYKmrVJ0wETViQ/01X7XuSo5HsreQlqbn8+DV3cgzyV2xW2G 3oYk8PEgGrG1MhHVdab3Is9XPUK1ZVoJ+5qYHGhs= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32U34NSG015551 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Mar 2023 22:04:23 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 29 Mar 2023 22:04:22 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 29 Mar 2023 22:04:22 -0500 Received: from [172.24.156.204] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32U34JQO012021; Wed, 29 Mar 2023 22:04:20 -0500 Message-ID: <48d7ba60-aa7b-8d93-fcf0-c7e64908e9f5@ti.com> Date: Thu, 30 Mar 2023 08:34:19 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [RFC PATCH 1/2] gpio: davinci: Do not clear the bank intr enable bit in save_context Content-Language: en-US To: Linus Walleij , Dhruva Gole CC: Vibhore Vardhan , Tony Lindgren , Vignesh , Bartosz Golaszewski , , , Devarsh Thakkar References: <20230323122910.991148-1-d-gole@ti.com> From: "J, KEERTHY" In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/28/2023 6:59 PM, Linus Walleij wrote: > On Thu, Mar 23, 2023 at 1:29 PM Dhruva Gole wrote: > >> The interrupt enable bits might be set if we want to use the GPIO as >> wakeup source. Clearing this will mean disabling of interrupts in the GPIO >> banks that we may want to wakeup from. >> Thus remove the line that was clearing this bit from the driver's save >> context function. >> >> Fixes: 0651a730924b ("gpio: davinci: Add support for system suspend/resume PM") >> Cc: Devarsh Thakkar >> Signed-off-by: Dhruva Gole > > Looks like the right solution to me. > I'm a bit surprised given how long we have had this driver. > I suppose people have used out-of-tree patches for suspend/resume. :( > > Reviewed-by: Linus Walleij Acked-by: Keerthy > > Yours, > Linus Walleij