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Wed, 20 May 2026 11:13:29 -0700 (PDT) X-Received: by 2002:a05:6a00:4c94:b0:834:e09b:de73 with SMTP id d2e1a72fcca58-83f33dda422mr13248414b3a.7.1779300809371; Wed, 20 May 2026 11:13:29 -0700 (PDT) Received: from [192.168.0.7] ([49.204.26.38]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f24cd0422sm26506189b3a.18.2026.05.20.11.13.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 May 2026 11:13:28 -0700 (PDT) Message-ID: <48e298d0-f4cb-4afb-8ba1-a6b39f3285cb@oss.qualcomm.com> Date: Wed, 20 May 2026 23:43:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] dt-bindings: arm: ras: Introduce bindings for ARM AEST To: Rob Herring Cc: Ruidong Tian , Tony Luck , Borislav Petkov , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, mark.rutland@arm.com, Sudeep Holla , linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> <20260505-aest-devicetree-support-v1-5-d5d6ffacf0a5@oss.qualcomm.com> <20260513175823.GA1471517-robh@kernel.org> Content-Language: en-US From: Umang Chheda In-Reply-To: <20260513175823.GA1471517-robh@kernel.org> Content-Type: text/plain; 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On 5/13/2026 11:28 PM, Rob Herring wrote: > On Tue, May 05, 2026 at 05:53:49PM +0530, Umang Chheda wrote: >> The Arm Error Source Table (AEST) specification describes how firmware >> exposes RAS error source topology to the operating system. On ACPI >> systems this information is provided via the AEST ACPI table. >> >> Introduce Device Tree bindings that provide an equivalent description >> of AEST error sources for DT-based platforms. >> >> Signed-off-by: Umang Chheda >> --- >> .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++++++++++ >> include/dt-bindings/arm/aest.h | 43 +++ >> 2 files changed, 449 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,aest.yaml b/Documentation/devicetree/bindings/arm/arm,aest.yaml >> new file mode 100644 >> index 000000000000..7809a0d38270 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/arm,aest.yaml >> @@ -0,0 +1,406 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/arm,aest.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Arm Error Source Table (AEST) >> + >> +maintainers: >> + - Umang Chheda >> + >> +description: >> + The Arm Error Source Table (AEST) describes RAS error sources and their >> + register interfaces. Each error source exposes one or more error records >> + through either system registers or a memory-mapped register window, and >> + may signal errors via interrupts. The top-level node acts as a container >> + for one or more child nodes, each describing a single AEST error source. >> + Refer to the Arm AEST specification (DEN0085 / DDI 0587B) for details. >> + Flag bit constants for use in DT source files are defined in >> + . >> + >> +properties: >> + compatible: >> + const: arm,aest >> + >> + "#address-cells": >> + const: 2 >> + >> + "#size-cells": >> + const: 2 >> + >> + ranges: true >> + >> +required: >> + - compatible >> + >> +additionalProperties: false >> + >> +patternProperties: >> + "^aest-[a-z0-9-]+(@[0-9a-f]+)?$": >> + type: object >> + description: >> + An AEST error source node describing one error source defined by >> + the Arm AEST specification. >> + >> + properties: >> + compatible: >> + description: >> + Identifies the type of AEST error source. Each value corresponds to >> + a distinct error source class defined by the Arm AEST specification. >> + arm,aest-proxy represents a proxy error source that forwards errors >> + from another error source. >> + enum: >> + - arm,aest-processor >> + - arm,aest-memory >> + - arm,aest-smmu >> + - arm,aest-gic >> + - arm,aest-pcie >> + - arm,aest-vendor >> + - arm,aest-proxy > > This is a fundamental difference how DT and ACPI get structured. ACPI > defines new table for some feature and puts everything in that table. > For DT, these all belong in the node for the corresponding h/w. For > example, if the GIC supports AEST, then that belongs in the GIC node. Thanks for the feedback. To clarify your suggestion — should the AEST RAS properties be added directly as properties of the hardware node (e.g. arm,ras-num-records inside the cpu@0 node itself), or as a child node under the hardware node (e.g. a ras-error-source {} child under cpu@0)? > >> + >> + reg: >> + description: >> + Register ranges for the error source. Absence of reg implies >> + system-register access (interface type 0). A single range implies >> + memory-mapped access (interface type 1). Two ranges imply >> + single-record memory-mapped access (interface type 2). >> + minItems: 1 >> + maxItems: 4 >> + >> + reg-names: >> + description: >> + Names for the register ranges. The base error-record window is >> + unnamed (or first entry). Optional named ranges provide access to >> + the fault-injection, error-group, and interrupt-config register >> + windows defined by the AEST specification. >> + minItems: 1 >> + maxItems: 4 >> + items: >> + enum: >> + - fault-inject >> + - err-group >> + - irq-config >> + >> + interrupts: >> + description: Interrupts associated with the error source. >> + minItems: 1 >> + maxItems: 2 >> + >> + interrupt-names: >> + description: Names of the interrupts associated with the error source. >> + minItems: 1 >> + maxItems: 2 >> + items: >> + enum: >> + - fhi >> + - eri >> + >> + arm,fhi-flags: >> + description: >> + Bitmask of flags for the fault-handling interrupt (FHI), as defined >> + in the AEST node interrupt structure flags field. Constants are >> + defined in - AEST_IRQ_MODE_LEVEL (0), >> + AEST_IRQ_MODE_EDGE (1). > > DT already has a way to define interrupt flags. Why invent something > new? Ack, this flag is not needed for DT based systems, will remove this. > > Rob Thanks, Umang