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Also Gary's patch has been >> reported to introduce regressions but it hasn't been reverted yet. Can you >> reply to that thread mentioning your patch, so everybody in the discussion >> is aware of your alternative proposal? > > Thanks for including me. I just tested this change and reverted my other > one (mtk_dsi) and confirm that it works on my Tungsten510 + SN65DSI83 + > tm070jdhg30 panel. > > Tested-by: Gary Bisson > > Note that the sn65dsi83 driver wasn't changed as I thought the PLL lock > in pre-enable was on purpose. It was introduced by Frieder with this > commit. Adding him to the thread to weigh in. > dd9e329af723 drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec Thanks for the mention. This was introduced to keep the init order according to the datasheet. The DSI host first needs to put the DSI lanes into the correct state in its pre_enable(). Then the bridge needs to be enabled (including the PLL) in the pre_enable() of the bridge driver. Only after that the DSI host is allowed to stream data. Moving the PLL init from pre_enable() to enable() probably violates this order. In the past this lead to sporadic issues with some hardware setups (depending on the display and the DSI host). Some of this is also described in the docs: [1] So from the first glance, I would assume this issue needs to be fixed in the DSI host driver. [1] https://docs.kernel.org/gpu/drm-kms-helpers.html#mipi-dsi-bridge-operation