Andi Kleen a écrit : >> oprofile_add_sample(regs, i); >> + /* >> + * We need to unmask the apic vector *before* >> + * writing reset_value to msr counter >> + */ >> + apic_write(APIC_LVTPC, APIC_DM_NMI); >> wrmsrl(msrs->counters[i].addr, -reset_value[i]); >> } >> } >> >> - /* Only P6 based Pentium M need to re-unmask the apic vector but it >> - * doesn't hurt other P6 variant */ >> - apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); > > Did you also test if it really needs to be inside the if () or > just before the wrmsrl? > Andi, the following patch also works well for me. The key is we must unmask APIC before the wrmsrl. after/before the rdmsrl has no impact. I wonder then if the final comment in ppro_check_ctrs() is still applicable. PATCH] oprofile: un-mask APIC before resetting counter in ppro_check_ctrs() While using oprofile on my HP BL460c G1, (two quad core intel E5450 CPU), I noticed that one CPU after the other could not get anymore NMI. After a while, all cores where blocked (ie not generating events for oprofile) I tried all major linux versions and all where affected by this freeze. I found that we have to un-mask APIC *before* writing to MSR counter when we get event notification, because we use APIC_LVTPC in edge triggered mode. Signed-off-by: Eric Dumazet --- arch/x86/oprofile/op_model_ppro.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-)