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([2600:8803:e7e4:1d00:4647:c57:a73c:39d8]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-73a28401fffsm219284a34.15.2025.06.13.07.20.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jun 2025 07:20:19 -0700 (PDT) Message-ID: <4923f49f-273f-4166-94bc-afe39618672c@baylibre.com> Date: Fri, 13 Jun 2025 09:20:18 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] dt-bindings: spi: zynqmp-qspi: Split the bus To: Sean Anderson , Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, "linux-iio@vger.kernel.org" , Jonathan Cameron , =?UTF-8?Q?Nuno_S=C3=A1?= References: <20250116232118.2694169-1-sean.anderson@linux.dev> <20250116232118.2694169-2-sean.anderson@linux.dev> <9f40295b-484a-48e8-b053-ff8550e589d7@baylibre.com> <46a7eba6-a705-4543-b967-e83ccc89e7d4@linux.dev> <6afc379a-2f9f-4462-ae30-ef6945a83236@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/12/25 6:44 PM, Sean Anderson wrote: > Hi David, > > I am (finally!) getting around to doing v2 of this series, and I ran > into a small problem with your proposed solution. > > On 1/23/25 16:59, David Lechner wrote: >> --- >> From: David Lechner >> Date: Thu, 23 Jan 2025 15:35:19 -0600 >> Subject: [PATCH 2/2] spi: add support for multi-bus controllers >> >> Add support for SPI controllers with multiple physical SPI buses. >> >> This is common in the type of controller that can be used with parallel >> flash memories, but can be used for general purpose SPI as well. >> >> To indicate support, a controller just needs to set ctlr->num_buses to >> something greater than 1. Peripherals indicate which bus they are >> connected to via device tree (ACPI support can be added if needed). >> >> In the future, this can be extended to support peripherals that also >> have multiple SPI buses to use those buses at the same time by adding >> a similar bus flags field to struct spi_transfer. >> >> Signed-off-by: David Lechner >> --- >> drivers/spi/spi.c | 26 +++++++++++++++++++++++++- >> include/linux/spi/spi.h | 13 +++++++++++++ >> 2 files changed, 38 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c >> index 10c365e9100a..f7722e5e906d 100644 >> --- a/drivers/spi/spi.c >> +++ b/drivers/spi/spi.c >> @@ -2364,7 +2364,7 @@ static void of_spi_parse_dt_cs_delay(struct device_node *nc, >> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, >> struct device_node *nc) >> { >> - u32 value, cs[SPI_CS_CNT_MAX]; >> + u32 value, buses[8], cs[SPI_CS_CNT_MAX]; >> int rc, idx; >> >> /* Mode (clock phase/polarity/etc.) */ >> @@ -2379,6 +2379,29 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, >> if (of_property_read_bool(nc, "spi-cs-high")) >> spi->mode |= SPI_CS_HIGH; >> >> + rc = of_property_read_variable_u32_array(nc, "spi-buses", buses, 1, >> + ARRAY_SIZE(buses)); >> + if (rc < 0 && rc != -EINVAL) { >> + dev_err(&ctlr->dev, "%pOF has invalid 'spi-buses' property (%d)\n", >> + nc, rc); >> + return rc; >> + } >> + >> + if (rc == -EINVAL) { >> + /* Default when property is omitted. */ >> + spi->buses = BIT(0); > > For backwards compatibility, the default bus for CS 1 on gqspi must be 1 > and not 0. Ideally there would be some hook for the master to fix things > up when the slaves are probed, but that doesn't seem to exist. I was > thinking about doing this with OF changesets. Do you have any better > ideas? > Does this work? spi->buses = BIT(cs[0]); (would have to move all the new code after cs[0] is assigned of course)