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From: Sudeep Holla <sudeep.holla@arm.com>
To: Lina Iyer <ilina@codeaurora.org>
Cc: Sudeep Holla <sudeep.holla@arm.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	open list <linux-kernel@vger.kernel.org>,
	linux-arm-msm@vger.kernel.org,
	Stephen Boyd <sboyd@codeaurora.org>,
	"Nayak, Rajendra" <rnayak@codeaurora.org>,
	asathyak@codeaurora.org
Subject: Re: [PATCH RFC 0/4] irqchip: qcom: add support for PDC interrupt controller
Date: Wed, 24 Jan 2018 10:10:35 +0000	[thread overview]
Message-ID: <494fa715-aff0-19f2-0ee9-78d8c0b33775@arm.com> (raw)
In-Reply-To: <20180123184442.GA12243@codeaurora.org>



On 23/01/18 18:44, Lina Iyer wrote:
> On Tue, Jan 23 2018 at 18:15 +0000, Sudeep Holla wrote:
>> Hi Lina,
>>
>> On Tue, Jan 23, 2018 at 5:56 PM, Lina Iyer <ilina@codeaurora.org> wrote:
>>> On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC
>>> is in a
>>> power domain that can be powered off when not needed. Interrupts that
>>> need to
>>> be sensed even when the GIC is powered off, are routed through an
>>> interrupt
>>> controller in an always-on domain called the Power Domain Controller
>>> a.k.a PDC.
>>> This series adds support for the PDC's interrupt controller.
>>>
>>
>> Sorry for the basic questions:
>>
>> 1. Will the GIC be powered off in any other state other than System
>> suspend ?
>>
> Yes. When all the CPUs are in idle, there is an opportunity to power off
> the CPU's power domain and the GIC. QCOM SoCs have been doing that for
> many generations now.
> 

OK interesting, in that case so either GIC state is saved/restored with
some out of tree patches or the firmware takes care of it and it's
transparent to Linux ?

Also when will this PDC wakeup interrupts get configured ?

>> 2. Why this needs to be done in Linux, why can't it be transparent and
>> hidden
>>    in the firmware doing the actual GIC power down ? I assume Linux is
>> not
>>    powering down the GIC.
> No. You are right, Linux is not powering off the GIC directly. A
> dedicated processor for power management in the SoC does that. Platform
> drivers in Linux, know and configure the wakeup interrupts (depending on
> the usecase). This is runtime specific and this is the way to tell the
> SoC to wake up the processor even if the GIC and the CPU domain were
> powered off.
> 

OK, understood. By transparent, I mean firmware can copy the interrupts
enabled in the GIC to the PDC. It need not be kernel driven.

>>
>> 3. I see some bits that enable secure interrupts in one of the patch.
>> Is that even
>>    safe to allow Linux to enable some secure interrupts in PDC ?
>>
> Linux should not and would not configure secure interrupts. We would not
> have permissions for secure interrupts. The interrupt names might be a
> misnomer, but the interrupts listed in patch #4 are all non-secure
> interrupts.
> 

OK. So I can assume PDC is partitioned in secure and non-secure. If not
it's safe not have any access for PDC in the kernel. Couple of designs
of similar PDC I have seen is system wide and does handle even secure
part of the system. That was the main reason for checking.

-- 
Regards,
Sudeep

  reply	other threads:[~2018-01-24 10:10 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-23 17:56 Lina Iyer
2018-01-23 17:56 ` [PATCH RFC 1/4] drivers: irqchip: pdc: " Lina Iyer
2018-01-24 14:20   ` Marc Zyngier
2018-01-25 18:52     ` Lina Iyer
2018-01-30 17:56     ` Lina Iyer
2018-01-30 18:11       ` Marc Zyngier
2018-01-31 16:24         ` Lina Iyer
2018-01-31 16:46           ` Marc Zyngier
2018-02-01 16:49             ` Lina Iyer
2018-01-23 17:56 ` [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Lina Iyer
2018-01-23 18:09   ` Sudeep Holla
2018-01-23 18:46     ` Lina Iyer
2018-01-24 14:24   ` Marc Zyngier
2018-01-30 15:20   ` Rob Herring
2018-01-23 17:56 ` [PATCH RFC 3/4] drivers: irqchip: pdc: log PDC info in FTRACE Lina Iyer
2018-01-23 18:13   ` Steven Rostedt
2018-01-25 15:45     ` Lina Iyer
2018-01-23 17:56 ` [PATCH RFC 4/4] drivers: irqchip: qcom: add pin information for SDM845 Lina Iyer
2018-01-24 14:20   ` Marc Zyngier
2018-01-25 18:14     ` Lina Iyer
2018-01-23 18:15 ` [PATCH RFC 0/4] irqchip: qcom: add support for PDC interrupt controller Sudeep Holla
2018-01-23 18:44   ` Lina Iyer
2018-01-24 10:10     ` Sudeep Holla [this message]
2018-01-24 17:43       ` Lina Iyer
2018-01-24 17:54         ` Sudeep Holla
2018-01-25 15:54           ` Lina Iyer
2018-01-25 16:39             ` Sudeep Holla
2018-01-25 18:13               ` Lina Iyer
2018-01-25 18:43                 ` Sudeep Holla
2018-01-25 20:05                   ` Lina Iyer
2018-01-26 11:39                     ` Sudeep Holla

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