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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59e5f56a476sm3269353e87.32.2026.02.16.06.56.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Feb 2026 06:56:16 -0800 (PST) Message-ID: <49540c43-894b-4d4c-8c46-4fe09d649729@oss.qualcomm.com> Date: Mon, 16 Feb 2026 15:56:13 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] phy: qcom: qmp-pcie: Skip PHY reset if already up To: Manivannan Sadhasivam , Dmitry Baryshkov Cc: Neil Armstrong , Krishna Chaitanya Chundru , Vinod Koul , Philipp Zabel , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260109-link_retain-v1-0-7e6782230f4b@oss.qualcomm.com> <20260109-link_retain-v1-1-7e6782230f4b@oss.qualcomm.com> <53f0c45f-7f5c-4abd-af84-cbb82d509872@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=c5WmgB9l c=1 sm=1 tr=0 ts=69933011 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gjtn7LuX9S0b4PncKSUA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-GUID: cxwvUYGg08rb4ltz4Zat99KalVqu2JE4 X-Proofpoint-ORIG-GUID: cxwvUYGg08rb4ltz4Zat99KalVqu2JE4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE2MDEyNyBTYWx0ZWRfXw1m6j0coRhfC 51HE2+I0QusyX3Bz29aIHpcrPILjURLV4f9kWb6YrS0uyO5Uicddo6zxmhSJmx1dL6nUT6wDb5V Q9kt8jX5pEIcMCwbAPb797WwT85AOXaavo8Lojrui/bKOKN5/zSvf5vUWHzRmUKo5NnXhxSPKDB UBV/myCsJJjdd6beJLXgqrhkPxzeZ9Ns/OcXSjDFT6XwG2aL8bJU9GxVaA07TyTzk74hV2A1/dT NW8CIUfUS1/vELkN3yQSREgoYr2LrT5+6fbBkcJ3na3S/C022L4xw3yPiKhpM3Y/gFuGChTTSJX VPcvoLoeFng0s+9FZc/KN4/Vz/q/RwFOvTGH/KfYIa4n48kpqCcoqbw8Fpi4oStR7lyKrV9oXn6 BGQ0lcxPtM7m9v5C+H2gI118CvUwFqEyo38h73EQv8tYD7XPsJNuELz19ThFn9vqqlKqcM/4+nM rcqVGOTU7LBKCjVjGFg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-16_04,2026-02-16_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 clxscore=1015 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602160127 On 2/16/26 3:53 PM, Manivannan Sadhasivam wrote: > On Fri, Jan 09, 2026 at 04:03:37PM +0200, Dmitry Baryshkov wrote: >> On Fri, Jan 09, 2026 at 02:10:49PM +0100, Neil Armstrong wrote: >>> On 1/9/26 14:08, Dmitry Baryshkov wrote: >>>> On Fri, Jan 09, 2026 at 12:51:06PM +0530, Krishna Chaitanya Chundru wrote: >>>>> If the bootloader has already powered up the PCIe PHY, doing a full >>>>> reset and waiting for it to come up again slows down boot time. >>>> >>>> How big is the delay caused by it? >>>> >>>>> >>>>> Add a check for PHY status and skip the reset steps when the PHY is >>>>> already active. In this case, only enable the required resources during >>>>> power-on. This works alongside the existing logic that skips the init >>>>> sequence. >>>> >>>> Can we end up in a state where the bootloader has mis-setup the link? Or >>>> the link going bad because of any glitch during the bootup? >>> >>> Good question, can we add a module parameter to force a full reset of the PHY in case >>> the bootloader is buggy ? >> >> I'd suggest a simpler thing: if the reset was skipped, reset the PHY in >> case of an error and retry. That's also one of the reasons why I asked >> for skip_reset not to be the persistent value. >> > > I'm not sure what value would resetting the PHY provide in the case of failure. > As per this patch, skip_reset is only going to be set for platforms where > bootloader has already configured the PHY. So in the case of PHY link failure, > simply resetting the PHY won't help IMO as the PHY register contents are going > to be presistent due to nocsr_reset. We can pull the not-nocsr_reset though? Konrad