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([2a0d:3344:2712:7e10:4d59:d956:544f:d65c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45624651a09sm30800535e9.12.2025.07.15.06.12.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 06:12:03 -0700 (PDT) Message-ID: <495a37e7-e31d-4671-a4d9-7e653ad80b60@redhat.com> Date: Tue, 15 Jul 2025 15:12:01 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 4/5] dpll: zl3073x: Add support to adjust phase To: Ivan Vecera , netdev@vger.kernel.org Cc: Prathosh Satish , Arkadiusz Kubalewski , Jiri Pirko , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, Michal Schmidt , Petr Oros References: <20250710153848.928531-1-ivecera@redhat.com> <20250710153848.928531-5-ivecera@redhat.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: <20250710153848.928531-5-ivecera@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/10/25 5:38 PM, Ivan Vecera wrote: > +static int > +zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, > + void *pin_priv, > + const struct dpll_device *dpll, > + void *dpll_priv, > + s32 *phase_adjust, > + struct netlink_ext_ack *extack) > +{ > + struct zl3073x_dpll *zldpll = dpll_priv; > + struct zl3073x_dev *zldev = zldpll->dev; > + struct zl3073x_dpll_pin *pin = pin_priv; > + u32 synth_freq; > + s32 phase_comp; > + u8 out, synth; > + int rc; > + > + out = zl3073x_output_pin_out_get(pin->id); > + synth = zl3073x_out_synth_get(zldev, out); > + synth_freq = zl3073x_synth_freq_get(zldev, synth); > + > + guard(mutex)(&zldev->multiop_lock); > + > + /* Read output configuration */ > + rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, > + ZL_REG_OUTPUT_MB_MASK, BIT(out)); > + if (rc) > + return rc; > + > + /* Read current output phase compensation */ > + rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, &phase_comp); > + if (rc) > + return rc; > + > + /* Value in register is expressed in half synth clock cycles */ > + phase_comp *= (int)div_u64(PSEC_PER_SEC, 2 * synth_freq); Is 'synth_freq' guaranteed to be != 0 even on extreme conditions? Possibly a comment or an explicit check could help. /P