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X-CSE-ConnectionGUID: 0WnlrJG/RkO9YT+a9bpoFw== X-CSE-MsgGUID: H4S8+IclTcmJkaFGlO3FpA== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="68847989" X-IronPort-AV: E=Sophos;i="6.20,256,1758610800"; d="scan'208";a="68847989" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2026 18:41:08 -0800 X-CSE-ConnectionGUID: ATzFmd2xTHeGxhnM0V9R+Q== X-CSE-MsgGUID: JyU03ysfTz6RYf+WEjLJPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,200,1763452800"; d="scan'208";a="201226730" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.240.14]) ([10.124.240.14]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2026 18:41:05 -0800 Message-ID: <496ac441-b8bf-44a4-a0de-d6e046f20a16@linux.intel.com> Date: Sun, 4 Jan 2026 10:41:02 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 10/13] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily To: Zide Chen , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Xudong Hao , Falcon Thomas References: <20251231224233.113839-1-zide.chen@intel.com> <20251231224233.113839-11-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20251231224233.113839-11-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/1/2026 6:42 AM, Zide Chen wrote: > Update event constraints base on the latest DMR uncore event list. > > Signed-off-by: Zide Chen > --- > V2: > - make use of the new UNCORE_EVENT_CONSTRAINT_RANGE > > arch/x86/events/intel/uncore_snbep.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c > index fac2be780276..3f96fcc8562b 100644 > --- a/arch/x86/events/intel/uncore_snbep.c > +++ b/arch/x86/events/intel/uncore_snbep.c > @@ -6660,10 +6660,19 @@ static const struct attribute_group dmr_cxlcm_uncore_format_group = { > .attrs = dmr_cxlcm_uncore_formats_attr, > }; > > +static struct event_constraint dmr_uncore_cxlcm_constraints[] = { > + UNCORE_EVENT_CONSTRAINT_RANGE(0x1, 0x24, 0x0f), > + UNCORE_EVENT_CONSTRAINT_RANGE(0x41, 0x41, 0xf0), > + UNCORE_EVENT_CONSTRAINT_RANGE(0x50, 0x5e, 0xf0), > + UNCORE_EVENT_CONSTRAINT_RANGE(0x60, 0x61, 0xf0), > + EVENT_CONSTRAINT_END > +}; > + > static struct intel_uncore_type dmr_uncore_cxlcm = { > .name = "cxlcm", > .event_mask = GENERIC_PMON_RAW_EVENT_MASK, > .event_mask_ext = DMR_CXLCM_EVENT_MASK_EXT, > + .constraints = dmr_uncore_cxlcm_constraints, > .format_group = &dmr_cxlcm_uncore_format_group, > .attr_update = uncore_alias_groups, > }; > @@ -6675,9 +6684,20 @@ static struct intel_uncore_type dmr_uncore_hamvf = { > .attr_update = uncore_alias_groups, > }; > > +static struct event_constraint dmr_uncore_cbo_constraints[] = { > + UNCORE_EVENT_CONSTRAINT(0x11, 0x1), > + UNCORE_EVENT_CONSTRAINT_RANGE(0x19, 0x1a, 0x1), > + UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), > + UNCORE_EVENT_CONSTRAINT(0x21, 0x1), > + UNCORE_EVENT_CONSTRAINT(0x25, 0x1), > + UNCORE_EVENT_CONSTRAINT(0x36, 0x1), > + EVENT_CONSTRAINT_END > +}; > + > static struct intel_uncore_type dmr_uncore_cbo = { > .name = "cbo", > .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT, > + .constraints = dmr_uncore_cbo_constraints, > .format_group = &dmr_sca_uncore_format_group, > .attr_update = uncore_alias_groups, > }; > @@ -6711,9 +6731,16 @@ static struct intel_uncore_type dmr_uncore_dda = { > .attr_update = uncore_alias_groups, > }; > > +static struct event_constraint dmr_uncore_sbo_constraints[] = { > + UNCORE_EVENT_CONSTRAINT(0x1f, 0x01), > + UNCORE_EVENT_CONSTRAINT(0x25, 0x01), > + EVENT_CONSTRAINT_END > +}; > + > static struct intel_uncore_type dmr_uncore_sbo = { > .name = "sbo", > .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT, > + .constraints = dmr_uncore_sbo_constraints, > .format_group = &dmr_sca_uncore_format_group, > .attr_update = uncore_alias_groups, > }; Reviewed-by: Dapeng Mi