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a="2921852" X-IronPort-AV: E=Sophos;i="6.27,199,1787036400"; d="scan'208";a="2921852" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2026 13:16:37 -0800 X-CSE-ConnectionGUID: zreB1KstRSWymL3NIunppg== X-CSE-MsgGUID: BxoBiPwHQe6ZVj1fLHo4og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,199,1787036400"; d="scan'208";a="7245091" Received: from soc-cp83kr3.clients.intel.com (HELO [10.122.184.228]) ([10.122.184.228]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2026 13:16:36 -0800 Message-ID: <49798d13-f426-4834-9996-5d8f1f7dad4c@intel.com> Date: Fri, 6 Nov 2026 15:16:35 -0600 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 03/18] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu To: Yosry Ahmed Cc: Sean Christopherson , Paolo Bonzini , Peter Zijlstra , kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao References: <20261106013927.166209-1-zide.chen@intel.com> <20261106013927.166209-4-zide.chen@intel.com> Content-Language: en-US From: "Chen, Zide" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit >> @@ -214,9 +214,15 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) >> >> pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1; >> >> - pmu->reserved_bits = 0xfffffff000280000ull; >> + /* >> + * AMD PerfEvtSeln registers do not support PinControl, and KVM does >> + * not emulate AnyThread due to cross-VM information leakage on SMT >> + * cores (as on the Intel side). >> + */ >> + pmu->eventsel_rsvd = GENMASK_ULL(63, 36) | ARCH_PERFMON_EVENTSEL_PIN_CONTROL | >> + ARCH_PERFMON_EVENTSEL_ANY; > > It's probably better if we diff against the generic pmu->eventsel_rsvd > set by kvm_pmu_refresh(), and explicitly add/remove bits as needed here, > like the Intel code. Then we also avoid re-iterating the AnyThread > rationale here. > > What do you think? Yes, I think this is better. How about this: diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index fb5a298244ec..15d4b94826f8 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -213,12 +213,11 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1; /* - * AMD PerfEvtSeln registers do not support PinControl, and KVM does - * not emulate AnyThread due to cross-VM information leakage on SMT - * cores (as on the Intel side). + * AMD PerfEvtSeln registers do not support PinControl, but support + * a 12-bit EventSelect (bits 35:32 in addition to 7:0). */ - pmu->eventsel_rsvd = GENMASK_ULL(63, 36) | ARCH_PERFMON_EVENTSEL_PIN_CONTROL | - ARCH_PERFMON_EVENTSEL_ANY; + pmu->eventsel_rsvd |= ARCH_PERFMON_EVENTSEL_PIN_CONTROL; + pmu->eventsel_rsvd &= ~AMD64_EVENTSEL_EVENT; if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && kvm_vcpu_has_mediated_pmu(vcpu)) pmu->eventsel_rsvd &= ~AMD64_EVENTSEL_HOST_GUEST_MASK; > > >> if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && kvm_vcpu_has_mediated_pmu(vcpu)) >> - pmu->reserved_bits &= ~AMD64_EVENTSEL_HOST_GUEST_MASK; >> + pmu->eventsel_rsvd &= ~AMD64_EVENTSEL_HOST_GUEST_MASK;