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Sun, 28 Jun 2026 22:20:57 -0700 (PDT) X-Received: by 2002:a05:7300:aca8:b0:304:70d0:4f03 with SMTP id 5a478bee46e88-30c858d23aamr12222738eec.6.1782710457322; Sun, 28 Jun 2026 22:20:57 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c7c4c691dsm39914896eec.5.2026.06.28.22.20.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Jun 2026 22:20:56 -0700 (PDT) Message-ID: <4980d925-ec32-4632-a377-d65b9ac1d152@oss.qualcomm.com> Date: Mon, 29 Jun 2026 10:50:50 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] arm64: dts: qcom: shikra: Add support for AudioCoreCC node To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com> <20260605-shikra-audiocorecc-v1-4-7ee6b5f2d928@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=F+FnsKhN c=1 sm=1 tr=0 ts=6a4200ba cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=SiY_No2TDSAPns8i4EEA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: 9YGyy56QsvdIS4bnAfGAJJ_s_S2SvVCT X-Proofpoint-ORIG-GUID: 9YGyy56QsvdIS4bnAfGAJJ_s_S2SvVCT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA0MyBTYWx0ZWRfX5PPAyAIQwhVt lv1nnYTXDq2dBnPYt4EpHr+EAGkgH7S78FW5xKp8BiY91MH611mQFSYwwTG2QoQpFIIBiTaDWtT 0hwlun/XmpY8EJq72pAB09DtuA6qTjQKEm4/H9uiL+l2sUfZzGnlEr6DocgoGbFHZ0QODXF0GLz E+5FilaLOjctnp/BS2ksfT9QH6Iq2MQJwkLLhomjlAV3CBW+bzZAZGKldc4W6zpIpufxmHJ39tu oxHBl9wDr15Lh0jGvenJtWthP/eotlBRJRNBdE9fespj/eJO7yGqwWgAOThyNwugvb5W9SfRH2A Zo+j5oIY6iNCrm+G8JVVKkZAb4iktqu7t3+zFZtxNe9UTC05hXWQjphnyULA5nJliY5WJ1rLSG8 qdWT8Bum0WvHEZia+HjXz4iVuwUjAlqxqE8G96PoEVFXbdCrJw2LqqcyJWtEY2D/5yb/n3oVQDP xyZEUm41SAY7HtXXEcw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA0MyBTYWx0ZWRfX4uqNggxNpasX 4r4Ulm/V65xFruW6+jSToevaDQflOvQ182DcK6F5RkSDcXWj4X1qyy8JmtP7LFafjvUGhGlckWu AiX1NjHGzMCN+5LPzZNC1CmeO5JESPc= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290043 On 11-06-2026 04:55 pm, Konrad Dybcio wrote: > On 6/5/26 1:26 PM, Imran Shaik wrote: >> Add support for Audio Core Clock Controller (AudioCoreCC) node on Qualcomm >> Shikra SoC. The CQM variant requires both clock and reset support, while >> the CQS variant requires only reset support. Update the respective device >> tree variants to enable and override the node as per variant requirements. >> >> Signed-off-by: Imran Shaik >> --- >> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 4 ++++ >> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 5 +++++ >> arch/arm64/boot/dts/qcom/shikra.dtsi | 13 +++++++++++++ >> 3 files changed, 22 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts >> index 0a52ab9b7a4c34d371f5ac23efe59d1c9d2723f4..0883c480bfbc80d7bead966b9ba932dee8a77bbf 100644 >> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts >> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts >> @@ -23,6 +23,10 @@ chosen { >> }; >> }; >> >> +&audiocorecc { >> + status = "okay"; >> +}; >> + >> &sdhc_1 { >> vmmc-supply = <&pm4125_l20>; >> vqmmc-supply = <&pm4125_l14>; >> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts >> index b3f19a64d7aed3121ef092df684b19a4de39b497..b5e3d573868a836ad5e5e8eb3024cb5fb71dbb4e 100644 >> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts >> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts >> @@ -23,6 +23,11 @@ chosen { >> }; >> }; >> >> +&audiocorecc { >> + compatible = "qcom,shikra-cqs-audiocorecc"; >> + status = "okay"; >> +}; >> + >> &sdhc_1 { >> vmmc-supply = <&pm4125_l20>; >> vqmmc-supply = <&pm4125_l14>; >> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi >> index a4334d99c1f35ee851ca8266ec37d4a200a07ee5..f15757d52af04d8cb5540354a239127cb0d174a3 100644 >> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi >> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi >> @@ -4,6 +4,7 @@ >> */ >> >> #include >> +#include >> #include >> #include >> #include >> @@ -640,6 +641,18 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, >> }; >> }; >> >> + audiocorecc: clock-controller@a0a0000 { >> + compatible = "qcom,shikra-cqm-audiocorecc"; >> + reg = <0x0 0x0a0a0000 0x0 0x10000>, > > This is called AUDIO_CORE_CC where seemingly all the clocks live > >> + <0x0 0x0a0b4000 0x0 0x1000>; > > and this is called AUDIO_CORE_CSR where seemingly all the resets live > > so it would make sense to split them Yes, the clocks and resets reside in different register spaces, I will split them into two different nodes as suggested. This will help to handle the CQM/CQS variants requirements more cleanly. Thanks, Imran