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[2001:1c00:c14:2800:ec23:a060:24d5:2453]) by smtp.gmail.com with ESMTPSA id r2sm1837777wma.1.2019.10.25.01.59.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Oct 2019 01:59:07 -0700 (PDT) Subject: Re: [PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver To: Andy Shevchenko Cc: "Rafael J . Wysocki" , Len Brown , Lee Jones , Mika Westerberg , linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org References: <20191024213827.144974-1-hdegoede@redhat.com> <20191024213827.144974-3-hdegoede@redhat.com> <20191025074154.GX32742@smile.fi.intel.com> From: Hans de Goede Message-ID: <49aa39b7-d457-1140-afdb-2a154278b29f@redhat.com> Date: Fri, 25 Oct 2019 10:59:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191025074154.GX32742@smile.fi.intel.com> Content-Language: en-US X-MC-Unique: Lfw5pdjXMEqwhHG1Vxy9YQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 25-10-2019 09:41, Andy Shevchenko wrote: > On Thu, Oct 24, 2019 at 11:38:25PM +0200, Hans de Goede wrote: >> Our current Crystal Cove OpRegion driver is only valid for the >> Crystal Cove PMIC variant found on Bay Trail (BYT) boards, >> Cherry Trail (CHT) based boards use another variant. >> >> At least the regulator registers are different on CHT and these register= s >> are one of the things controlled by the custom PMIC OpRegion. >> >> Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell >> configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT >> devices by removing the "crystal_cove_pmic" MFD cell on CHT devices. >> >> This commit renames the intel_pmic_crc.c driver and the cell to be >> prefixed with "byt" to indicate that this code is for BYT devices only. >> >> This is a preparation patch for adding a separate PMIC OpRegion >> driver for the CHT variant of the Crystal Cove PMIC (sometimes called >> Crystal Cove Plus in Android kernel sources). >=20 >> .../acpi/pmic/{intel_pmic_crc.c =3D> intel_pmic_bytcrc.c} | 4 ++-- >> drivers/mfd/intel_soc_pmic_crc.c | 2 +- >=20 > I would go with previously established pattern, i.e. intel_pmic_bytcc.c. Well that would be consistent with the chtwc for the Whiskey Cove, but Crystal Cove related files are shortened to crc in many places already: Filenames before this patch: drivers/acpi/pmic/intel_pmic_crc.c drivers/pwm/pwm-crc.c drivers/mfd/intel_soc_pmic_crc.c And to me "cc" stands for the Type-C cc lines, or for Cc: from email, so IMHO it is best to stick with crc here. >> +++ b/drivers/mfd/intel_soc_pmic_crc.c >> @@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] =3D { >> =09=09.resources =3D gpio_resources, >> =09}, >> =09{ >> -=09=09.name =3D "crystal_cove_pmic", >> +=09=09.name =3D "byt_crystal_cove_pmic", >> =09}, >> =09{ >> =09=09.name =3D "crystal_cove_pwm", >=20 > I'm wondering shouldn't we rename the PWM and GPIO for the sake of consis= tency? > Yes, if a driver is used on both CHT and BYT, let it provide two names. I believe it is fine to keep the blocks which are identical between the 2 versions as just "crystal_cove_foo", but renaming them is fine with m= e too, but that follows outside the scope of this series and should be done in a follow-up series IMHO. Regards, Hans