Re: [PATCH 00/17] Add support for DU and DSI on the Renesas RZ/V2H(P) SoC

[Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>]

Hi,

On 31/03/2025 00:06, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This patch series adds support for the Display Unit (DU) and MIPI DSI
> interface on the Renesas RZ/V2H(P) SoC. The inital patches add PLLDSI
> clocks and reset entries for the DSI and LCDC and the later patches add
> support for the DU and DSI drivers. The DU block is similar to the
> RZ/G2L SoC, but the DSI interface is slightly different. The patches
> include updates to the device tree bindings, clock and reset
> controllers, and the DU driver to accommodate these changes.
> 
> Note, my initail intention was to split the clock patches and the DU/DSI
> driver patches into two separate series. However, I found that sending
> them together will make it easier for the reviewers to understand clock
> related changes.
> 
> Note, the clock patches aplly on top of the following patch series:
> - https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> - https://lore.kernel.org/all/20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

This is missing dri-devel list from the to/cc. Did you use 
scripts/get_maintainer.pl?

  Tomi

> Cheers,
> Prabhakar
> 
> Lad Prabhakar (17):
>    clk: renesas: rzv2h-cpg: Add support for DSI clocks
>    clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC
>    media: dt-bindings: media: renesas,vsp1: Document RZ/V2H(P)
>    media: dt-bindings: media: renesas,fcp: Document RZ/V2H(P) SoC
>    dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC
>    dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P)
>      SoC
>    drm: renesas: rz-du: Add support for RZ/V2H(P) SoC
>    drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range
>    drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation
>    drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation
>    drm: renesas: rz-du: mipi_dsi: Add OF data support
>    drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency
>      calculations
>    drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support
>    drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for
>      RZ/V2H(P)
>    drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring
>      VCLK and mode validation
>    drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling
>    drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC
> 
>   .../bindings/display/bridge/renesas,dsi.yaml  | 117 +++-
>   .../bindings/display/renesas,rzg2l-du.yaml    |  28 +-
>   .../bindings/media/renesas,fcp.yaml           |   2 +
>   .../bindings/media/renesas,vsp1.yaml          |   1 +
>   drivers/clk/renesas/r9a09g057-cpg.c           |  63 ++
>   drivers/clk/renesas/rzv2h-cpg.c               | 284 ++++++++
>   drivers/clk/renesas/rzv2h-cpg.h               |  17 +
>   drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  |  11 +
>   .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 607 +++++++++++++++++-
>   .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h   |  42 +-
>   include/linux/clk/renesas-rzv2h-dsi.h         | 207 ++++++
>   11 files changed, 1309 insertions(+), 70 deletions(-)
>   create mode 100644 include/linux/clk/renesas-rzv2h-dsi.h
>