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Mon, 08 Jun 2026 14:55:07 -0700 (PDT) X-Received: by 2002:a05:6a00:844:b0:835:405a:7e6d with SMTP id d2e1a72fcca58-842b0ea14f4mr17787832b3a.21.1780955706571; Mon, 08 Jun 2026 14:55:06 -0700 (PDT) Received: from [192.168.1.7] ([106.222.228.237]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282221470sm20386450b3a.6.2026.06.08.14.55.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 14:55:06 -0700 (PDT) Message-ID: <49b8530f-24d3-4201-b22c-0f8eaea9f4e0@oss.qualcomm.com> Date: Tue, 9 Jun 2026 03:24:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/6] drm/msm/a6xx: Fix IRQ storm during msm_recovery test To: rob.clark@oss.qualcomm.com Cc: Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Puranam V G Tejaswi , Jie Zhang , =?UTF-8?Q?Ma=C3=ADra_Canal?= , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jie Zhang References: <20260605-assorted-fixes-june-v1-0-2caa04f7287c@oss.qualcomm.com> <20260605-assorted-fixes-june-v1-5-2caa04f7287c@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: n0vrRCIiwDonJhl21_HdWBoYt9TyN79d X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDIwMCBTYWx0ZWRfXzyPpEzIoSdl1 5ajIsOG3JH5CwTnZktmlc78a0y5gQh5U2+UMav4Iq36KHGFVuuAaMT57SSp9VRXxoVvBhtaNqCC QofeSEBNNY3WaQUlTSSscHwdYRLjd8DNx4xDb3wZTVCDt7slyJZWpo1hxwHQqX1BPsrDmkZjQCT PTAa25GgJ1L4ejjJCHfcCo7m6ivn6wkjpMOlriZlaZeFBbpwgD4U3Ff7yBKTwno+nDgJiJ7BLSC 4OuWSb+0ApBDyO+KcNz82/+yZ0g7szZTnMyESwLiC6ZXTI5an0n0ZZNbZBf1WxIfBNFg4JbYbNZ Fvx/20hzku3qvkecJdAInaWlOQJtloUjmgEzOG+QNEokaYjzl7+LTQwdO3ZA6Jiht19BxRkxqep YzlPtiwInJHPiNLlNv8Hy31lnRBz3W1/WVtLlytI0aMrOEtfUCvKxZBjnblwthwzENQuUohGUY6 hk0FrjROTB/N0K9bHJA== X-Authority-Analysis: v=2.4 cv=XKAAjwhE c=1 sm=1 tr=0 ts=6a273a3c cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Q2jhz0oZVy1Wt6PcVz7aQg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=WJmIXLFun9vGvqKifugA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: n0vrRCIiwDonJhl21_HdWBoYt9TyN79d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_05,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080200 On 6/5/2026 12:20 PM, Rob Clark wrote: > On Thu, Jun 4, 2026 at 1:10 PM Akhil P Oommen wrote: >> >> From: Jie Zhang >> >> Once a hang is triggered by the msm_recovery test, the gpu error irq >> remains asserted and triggers an interrupt storm. In the worst case, >> this IRQ storm lands on the CPU core where the hangcheck timer is >> scheduled, blocking it from running. This eventually leads to CPU >> watchdog timeouts. >> >> To fix this, mask the gpu error irqs during msm_recovery test and >> enable them back during the recovery. >> >> Fixes: 5edf2750d998 ("drm/msm: Add debugfs to disable hw err handling") >> Signed-off-by: Jie Zhang >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 5 +++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++++- >> drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 5 ++++- >> drivers/gpu/drm/msm/msm_gpu.c | 2 ++ >> 4 files changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >> index 2c0bbac43c52..f1df2514c613 100644 >> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >> @@ -1275,6 +1275,11 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu) >> status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR); >> >> if (priv->disable_err_irq) { >> + /* Turn off interrupts to avoid interrupt storm */ >> + gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, >> + A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | >> + A5XX_RBBM_INT_0_MASK_CP_SW); >> + >> status &= A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | >> A5XX_RBBM_INT_0_MASK_CP_SW; >> } >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 8b3bb2fd433b..9a4f9d0e1780 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1911,8 +1911,11 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) >> >> gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); >> >> - if (priv->disable_err_irq) >> + if (priv->disable_err_irq) { >> + /* Turn off interrupts to avoid interrupt storm */ >> + gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS); >> status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; >> + } >> >> if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) >> a6xx_fault_detect_irq(gpu); >> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> index 9e44fd1ae634..0f6fd35bd587 100644 >> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> @@ -1211,8 +1211,11 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu) >> >> gpu_write(gpu, REG_A8XX_RBBM_INT_CLEAR_CMD, status); >> >> - if (priv->disable_err_irq) >> + if (priv->disable_err_irq) { >> + /* Turn off interrupts to avoid interrupt storm */ >> + gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS); >> status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; >> + } >> >> if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) >> a8xx_fault_detect_irq(gpu); >> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c >> index 9ac7740a87f0..48ac51f4119b 100644 >> --- a/drivers/gpu/drm/msm/msm_gpu.c >> +++ b/drivers/gpu/drm/msm/msm_gpu.c >> @@ -552,6 +552,8 @@ static void recover_worker(struct kthread_work *work) >> msm_update_fence(ring->fctx, fence); >> } >> >> + priv->disable_err_irq = false; > > Ok, so we rely on recovery to re-enable the error irqs.. that is > probably ok, given the intended purpose of the debugfs file. And, > well, it is debugfs. But why do we clear disable_err_irq here? Now that we are updating the IRQ mask register which won't reset until there is a gpu suspend, its side effect will be felt even after userspace deasserts the debugfs knob, potentially into the next testcase. This is different from the older behavior. So, I felt it would be better to reset this flag during the recovery, considering msm_recovery is the only user of this knob, afaiu. I should have explicitly called out this new behavior of disable_err_irq in the commit text, but I forgot. -Akhil. > > BR, > -R > >> + >> gpu->funcs->recover(gpu); >> >> /* retire completed submits, plus the one that hung: */ >> >> -- >> 2.51.0 >>