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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76917db770sm10549869a12.32.2026.03.31.23.46.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Mar 2026 23:46:58 -0700 (PDT) Message-ID: <49dae108-ad9d-4931-a10e-810de5766790@oss.qualcomm.com> Date: Wed, 1 Apr 2026 14:46:45 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 18/38] drm/msm/dp: Add support to enable MST in mainlink control To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20250825-msm-dp-mst-v3-0-01faacfcdedd@oss.qualcomm.com> <20250825-msm-dp-mst-v3-18-01faacfcdedd@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Qk0dkTuC1XjNbtrN_UZ32IUmmwjOSAyX X-Proofpoint-ORIG-GUID: Qk0dkTuC1XjNbtrN_UZ32IUmmwjOSAyX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDA1OCBTYWx0ZWRfX4VRjSn/ZLn32 th0I7f3izO02dY/t6V55KR2QO3qGYnAXXY/pc12yk2bhZ/CHt51F7RPrffUFtIWDMwT1WIrY5LA fGU6rPi02lOacZTXDMYYw3lWYKqoKj/W/XH5kLiCxhQbuifhMdB2BqGT3u4paPGpcLz9dZR17J5 ae8DBHh3dw38o2iT+74AxeOiDVO6ovRjleVIDMg1PXHKJdGuv8PSsYUrRh+givX/fZU9GErIagu 0vdpj52tc8Oo507T7HOwu49MGEORbwTjQLMueB3MoVS2e9MBKClZXccC+TokBT405xbLUV7m/d5 PdT3c44S2cfun+Fcv3m2cV4xvp6ILs3AufARDd9tQiOEpjwqMH/ps8wWyyDSkEyi44Bfu+n/fY2 gVDGBeuwHS0eonSD9BYPUh8qaBqLhbVA+6aChC7iimAzsTogc3SFkfP1cQb0Uu/sZYMCPFYu2FD yp1T4TEJO3Uo8sIAqXA== X-Authority-Analysis: v=2.4 cv=aJT9aL9m c=1 sm=1 tr=0 ts=69ccbf64 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=0OcOfTFRHD3XvKAs1WQA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_02,2026-03-31_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010058 On 8/26/2025 5:24 AM, Dmitry Baryshkov wrote: > On Mon, Aug 25, 2025 at 10:16:04PM +0800, Yongxing Mou wrote: >> From: Abhinav Kumar >> >> Add support to program the MST enable bit in the mainlink control >> register when an MST session is active or being disabled. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++ >> drivers/gpu/drm/msm/dp/dp_reg.h | 1 + >> 2 files changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h >> index de3d0b8b52c269fd7575edf3f4096a4284ad0b8d..fda847b33f8d0d6ec4d2589586b5a3d6c9b1ccf3 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_reg.h >> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h >> @@ -128,6 +128,7 @@ >> #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1) >> #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3) >> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) >> +#define DP_MAINLINK_CTRL_MST_EN (0x04000100) > > Why are there two bits? > Bit 8 enables MST, and bit 26 was set to select the required ECF endianness. 27:26 ECF_MODE MST ECF Endianness 0x0: [63:56], [55:48], ... [7:0] 0x1: [7:0], [15:8], ... [63:56] 0x2: [56:63], [48:55], ... [0:7] 0x3: [0:7], [8:15], ... [56:63] 8 MST_EN Multi Stream Enable >> >> #define REG_DP_STATE_CTRL (0x00000004) >> #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) >> >> -- >> 2.34.1 >> >