From: "H. Peter Anvin" <hpa@zytor.com>
To: Jack Steiner <steiner@sgi.com>
Cc: Chris Friesen <cfriesen@nortel.com>,
Daniel Walker <dwalker@fifo99.com>,
mingo@elte.hu, tglx@linutronix.de, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] x86: SGU UV Add volatile semantics to macros that access chipset registers
Date: Wed, 09 Sep 2009 20:05:30 -0700 [thread overview]
Message-ID: <4AA86CFA.8090000@zytor.com> (raw)
In-Reply-To: <20090910022226.GB10038@sgi.com>
On 09/09/2009 07:22 PM, Jack Steiner wrote:
> Add volatile-semantics to the SGI UV read/write macros that are
> used to access chipset memory mapped registers. No direct
> references to volatile are made. Instead the readq/writeq
> macros are used.
>
> Signed-off-by: Jack Steiner <steiner@sgi.com>
The -q part of readq/writeq is qword, 64 bits. It looks like you're
replacing references of other sizes with qword references; was that
intended?
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
next prev parent reply other threads:[~2009-09-10 3:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-09 15:42 [PATCH] x86: SGU UV Add volatile " Jack Steiner
2009-09-09 16:10 ` Daniel Walker
2009-09-09 18:01 ` Jack Steiner
2009-09-09 18:11 ` Daniel Walker
2009-09-09 18:54 ` Chris Friesen
2009-09-09 19:38 ` Jack Steiner
2009-09-10 0:44 ` H. Peter Anvin
2009-09-10 2:21 ` Jack Steiner
2009-09-10 2:22 ` [PATCH V2] x86: SGU UV Add volatile semantics " Jack Steiner
2009-09-10 3:05 ` H. Peter Anvin [this message]
2009-09-10 3:23 ` Jack Steiner
2009-09-10 14:31 ` [PATCH V3] " Jack Steiner
2009-09-18 12:06 ` [tip:x86/urgent] x86: SGI UV: " tip-bot for Jack Steiner
2009-09-09 19:20 ` [PATCH] x86: SGU UV Add volatile " Jack Steiner
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