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From: "H. Peter Anvin" <hpa@zytor.com>
To: "Ahmed S. Darwish" <darwi@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	John Ogness <john.ogness@linutronix.de>,
	x86@kernel.org, x86-cpuid@lists.linux.dev,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 19/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.3
Date: Wed, 12 Mar 2025 12:54:31 -0700	[thread overview]
Message-ID: <4BCBA481-AC3A-4A65-B791-235E580286CC@zytor.com> (raw)
In-Reply-To: <20250312143738.458507-20-darwi@linutronix.de>

On March 12, 2025 7:37:36 AM PDT, "Ahmed S. Darwish" <darwi@linutronix.de> wrote:
>Update kcpuid's CSV file to version 2.3, as generated by x86-cpuid-db.
>
>Summary of the v2.3 changes:
>
>* Per H. Peter Anvin's feedback, leaf 0x3 is not unique to Transmeta as
>  the CSV file earlier claimed.  Since leaf 0x3's format differs between
>  Intel and Transmeta, and the project does not yet support having the
>  same CPUID bitfield with varying interpretations across vendors, leaf
>  0x3 is removed for now.  Given that Intel discontinued support for PSN
>  from Pentium 4 onward, and Linux force disables it on early boot for
>  privacy concerns, this should have minimal impact.
>
>* Leaf 0x80000021: Make bitfield IDs and descriptions coherent with each
>  other.  Remove "_support" from bitfield IDs, as no other leaf has such
>  convention.
>
>Reported-by: "H. Peter Anvin" <hpa@zytor.com>
>Closes: https://lkml.kernel.org/r/C7684E03-36E0-4D58-B6F0-78F4DB82D737@zytor.com
>Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
>Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.3/CHANGELOG.rst
>---
> tools/arch/x86/kcpuid/cpuid.csv | 30 +++++++++++-------------------
> 1 file changed, 11 insertions(+), 19 deletions(-)
>
>diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
>index 9613e09cbfb3..8d25b0b49f3b 100644
>--- a/tools/arch/x86/kcpuid/cpuid.csv
>+++ b/tools/arch/x86/kcpuid/cpuid.csv
>@@ -1,5 +1,5 @@
> # SPDX-License-Identifier: CC0-1.0
>-# Generator: x86-cpuid-db v2.2
>+# Generator: x86-cpuid-db v2.3
> 
> #
> # Auto-generated file.
>@@ -116,14 +116,6 @@
>        0x2,         0,  edx,   30:24,    desc15                 , Descriptor #15
>        0x2,         0,  edx,      31,    edx_invalid            , Descriptors 12-15 are invalid if set
> 
>-# Leaf 3H
>-# Transmeta Processor Serial Number (PSN)
>-
>-       0x3,         0,  eax,    31:0,    cpu_psn_0              , Processor Serial Number bytes 0 - 3
>-       0x3,         0,  ebx,    31:0,    cpu_psn_1              , Processor Serial Number bytes 4 - 7
>-       0x3,         0,  ecx,    31:0,    cpu_psn_2              , Processor Serial Number bytes 8 - 11
>-       0x3,         0,  edx,    31:0,    cpu_psn_3              , Processor Serial Number bytes 12 - 15
>-
> # Leaf 4H
> # Intel deterministic cache parameters
> 
>@@ -1020,20 +1012,20 @@
> 0x80000021,         0,  eax,       0,    no_nested_data_bp      , No nested data breakpoints
> 0x80000021,         0,  eax,       1,    fsgs_non_serializing   , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
> 0x80000021,         0,  eax,       2,    lfence_rdtsc           , LFENCE always serializing / synchronizes RDTSC
>-0x80000021,         0,  eax,       3,    smm_page_cfg_lock      , SMM paging configuration lock is supported
>+0x80000021,         0,  eax,       3,    smm_page_cfg_lock      , SMM paging configuration lock
> 0x80000021,         0,  eax,       6,    null_sel_clr_base      , Null selector clears base
>-0x80000021,         0,  eax,       7,    upper_addr_ignore      , EFER MSR Upper Address Ignore Enable bit supported
>-0x80000021,         0,  eax,       8,    autoibrs               , EFER MSR Automatic IBRS enable bit supported
>-0x80000021,         0,  eax,       9,    no_smm_ctl_msr         , SMM_CTL MSR (0xc0010116) is not present
>-0x80000021,         0,  eax,      10,    fsrs_supported         , Fast Short Rep STOSB (FSRS) is supported
>-0x80000021,         0,  eax,      11,    fsrc_supported         , Fast Short Rep CMPSB (FSRC) is supported
>-0x80000021,         0,  eax,      13,    prefetch_ctl_msr       , Prefetch control MSR is supported
>+0x80000021,         0,  eax,       7,    upper_addr_ignore      , EFER MSR Upper Address Ignore
>+0x80000021,         0,  eax,       8,    autoibrs               , EFER MSR Automatic IBRS
>+0x80000021,         0,  eax,       9,    no_smm_ctl_msr         , SMM_CTL MSR (0xc0010116) is not available
>+0x80000021,         0,  eax,      10,    fsrs                   , Fast Short Rep STOSB
>+0x80000021,         0,  eax,      11,    fsrc                   , Fast Short Rep CMPSB
>+0x80000021,         0,  eax,      13,    prefetch_ctl_msr       , Prefetch control MSR is available
> 0x80000021,         0,  eax,      16,    opcode_reclaim         , Reserves opcode space
> 0x80000021,         0,  eax,      17,    user_cpuid_disable     , #GP when executing CPUID at CPL > 0 is supported
>-0x80000021,         0,  eax,      18,    epsf_supported         , Enhanced Predictive Store Forwarding (EPSF) is supported
>+0x80000021,         0,  eax,      18,    epsf                   , Enhanced Predictive Store Forwarding
> 0x80000021,         0,  eax,      22,    wl_feedback            , Workload-based heuristic feedback to OS
>-0x80000021,         0,  eax,      24,    eraps_support          , Enhanced Return Address Predictor Security
>-0x80000021,         0,  eax,      27,    sbpb                   , Support for the Selective Branch Predictor Barrier
>+0x80000021,         0,  eax,      24,    eraps                  , Enhanced Return Address Predictor Security
>+0x80000021,         0,  eax,      27,    sbpb                   , Selective Branch Predictor Barrier
> 0x80000021,         0,  eax,      28,    ibpb_brtype            , Branch predictions flushed from CPU branch predictor
> 0x80000021,         0,  eax,      29,    srso_no                , CPU is not subject to the SRSO vulnerability
> 0x80000021,         0,  eax,      30,    srso_uk_no             , CPU is not vulnerable to SRSO at user-kernel boundary

As I said, you can simply treat leaf 3 as raw 128-bit hexadecimal number; there really isn't a need to "interpret" it since the only meaningful use of it is as a unique identifier combined with vendor-FMS.

  reply	other threads:[~2025-03-12 19:55 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-12 14:37 [PATCH v2 00/20] tools/x86/kcpuid: x86-cpuid-db v2.3 update Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 01/20] tools/x86/kcpuid: Fix error handling Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 02/20] tools/x86/kcpuid: Exit the program on invalid parameters Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 03/20] tools/x86/kcpuid: Simplify usage() handling Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 04/20] tools/x86/kcpuid: Save CPUID output in an array Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 05/20] tools/x86/kcpuid: Print correct CPUID output register names Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 06/20] tools/x86/kcpuid: Remove unused local variable Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 07/20] tools/x86/kcpuid: Remove unused global variable Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 08/20] tools/x86/kcpuid: Set function return type to void Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 09/20] tools/x86/kcpuid: Use C99-style for loops Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 10/20] tools/x86/kcpuid: Use <cpuid.h> intrinsics Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 11/20] tools/x86/kcpuid: Refactor CPUID range handling for future expansion Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 12/20] tools/x86/kcpuid: Extend CPUID index mask macro Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 13/20] tools/x86/kcpuid: Consolidate index validity checks Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 14/20] tools/x86/kcpuid: Filter valid CPUID ranges Ahmed S. Darwish
2025-03-12 15:18   ` Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 15/20] tools/x86/kcpuid: Define Transmeta and Centaur index ranges Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 16/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0 Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 17/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.1 Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 18/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2 Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 19/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.3 Ahmed S. Darwish
2025-03-12 19:54   ` H. Peter Anvin [this message]
2025-03-19 11:55     ` Ahmed S. Darwish
2025-03-12 14:37 ` [PATCH v2 20/20] MAINTAINERS: Include kcpuid under X86 CPUID DATABASE Ahmed S. Darwish

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