From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x227IyTtAxjqy0mv8Xgfoy0xQ2EK5WiOqRNHK6sC3dLwitD207dt4QY6vN5428F/3c9p7ItMr ARC-Seal: i=1; a=rsa-sha256; t=1517170885; cv=none; d=google.com; s=arc-20160816; b=JvW2Vi/E3nLh6jL1dS0aPTBiBms7vfV3k2l2PD+g1QqDNr6wg3o+Px6q/sDVISlfnB jQvraLqG6hZqbsFtxniblH6cDSNcGsTcch3wrNAiCedzjfffpHav29gV1YmiPjFZmIRb LO81R9rInJ6ORzQmz3iSuVGiOE6Hn6ZWqE8fUU+3TLFuHb+hFEuM6D0B+cX2ZIbyhAZd BDy7mgJeVB8KTASb9ANEEXD93AdZ7IdDOq3OxVvhLqlAOWgUnLP2O4DLCCDyrMk8/uEa b2/5vsoculM6Q7LceodP2rwtTEO8G3N+l+60OzrN3aZRLP4/VUQ3JzMxMMPDN8CNmdkh 6/LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:from:cc:to:subject:content-transfer-encoding :mime-version:references:in-reply-to:user-agent:date:dkim-signature :arc-authentication-results; bh=zKQAcm+Uqo0vyHhitSmLwaGQSaXMs+xiORN+i0tSH/A=; b=r3b3tFUtjFL7mWGdH3+9K8/0IFx25vDtTk6XvVipXCMnnrJ4EPnUs7TMgQ8FWzVkA0 l9J7n/odJVnPUUjlL8PnavzfWxNu/ZEFByekgJpbgH8FLgfv8DQR1vPffZR6Fx7kytL/ +fIkjTUXW8GenWOhQGf9K/lkplpRsxiF8rmLDnrR4ElFOHLVFPfihKvlJAM2nWJw2eMg ND4hTwyfjOMtEmQzuv/75twB+W53bCgKW3eUaGkJ71aIp57mgaSy04/RP27+WceK9Rj7 Ex4LFgxufww+9EhG8Et+XwDs0lGleVSUjV7WRlFcIuNoRQry7MmKWv64DpIfcBs3vj/d 6WwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@oracle.com header.s=corp-2017-10-26 header.b=UuoT3lD9; spf=pass (google.com: domain of konrad.wilk@oracle.com designates 141.146.126.79 as permitted sender) smtp.mailfrom=konrad.wilk@oracle.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=oracle.com Authentication-Results: mx.google.com; dkim=pass header.i=@oracle.com header.s=corp-2017-10-26 header.b=UuoT3lD9; spf=pass (google.com: domain of konrad.wilk@oracle.com designates 141.146.126.79 as permitted sender) smtp.mailfrom=konrad.wilk@oracle.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=oracle.com Date: Sun, 28 Jan 2018 15:21:01 -0500 User-Agent: K-9 Mail for Android In-Reply-To: <1517167750-23485-1-git-send-email-karahmed@amazon.de> References: <1517167750-23485-1-git-send-email-karahmed@amazon.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH] x86: vmx: Allow direct access to MSR_IA32_SPEC_CTRL To: KarimAllah Ahmed , kvm@vger.kernel.org, linux-kernel@vger.kernel.org CC: Asit Mallick , Arjan Van De Ven , Dave Hansen , Andi Kleen , Andrea Arcangeli , Linus Torvalds , Tim Chen , Thomas Gleixner , Dan Williams , Jun Nakajima , Paolo Bonzini , David Woodhouse , Greg KH , Andy Lutomirski , Ashok Raj , daniel.kiper@oracle.com From: Konrad Rzeszutek Wilk Message-ID: <4DCAF18F-C86A-4CBC-A9CC-CC01BF63313F@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8788 signatures=668655 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1801280283 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590865729989295970?= X-GMAIL-MSGID: =?utf-8?q?1590868977686236504?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On January 28, 2018 2:29:10 PM EST, KarimAllah Ahmed = wrote: >Add direct access to MSR_IA32_SPEC_CTRL for guests=2E This is needed for >guests >that will only mitigate Spectre V2 through IBRS+IBPB and will not be >using a >retpoline+IBPB based approach=2E > >To avoid the overhead of atomically saving and restoring the >MSR_IA32_SPEC_CTRL >for guests that do not actually use the MSR, only add_atomic_switch_msr >when a >non-zero is written to it=2E We tried this and found that it was about 3% slower that doing the old way= of rdmsr and wrmsr=2E But that was also with the host doing IBRS as well=2E On what type of hardware did you run this? Ccing Daniel=2E > >Cc: Asit Mallick >Cc: Arjan Van De Ven >Cc: Dave Hansen >Cc: Andi Kleen >Cc: Andrea Arcangeli >Cc: Linus Torvalds >Cc: Tim Chen >Cc: Thomas Gleixner >Cc: Dan Williams >Cc: Jun Nakajima >Cc: Paolo Bonzini >Cc: David Woodhouse >Cc: Greg KH >Cc: Andy Lutomirski >Signed-off-by: KarimAllah Ahmed >Signed-off-by: Ashok Raj >--- > arch/x86/kvm/cpuid=2Ec | 4 +++- > arch/x86/kvm/cpuid=2Eh | 1 + >arch/x86/kvm/vmx=2Ec | 63 >++++++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 67 insertions(+), 1 deletion(-) > >diff --git a/arch/x86/kvm/cpuid=2Ec b/arch/x86/kvm/cpuid=2Ec >index 0099e10=2E=2Edc78095 100644 >--- a/arch/x86/kvm/cpuid=2Ec >+++ b/arch/x86/kvm/cpuid=2Ec >@@ -70,6 +70,7 @@ u64 kvm_supported_xcr0(void) > /* These are scattered features in cpufeatures=2Eh=2E */ > #define KVM_CPUID_BIT_AVX512_4VNNIW 2 > #define KVM_CPUID_BIT_AVX512_4FMAPS 3 >+#define KVM_CPUID_BIT_SPEC_CTRL 26 > #define KF(x) bit(KVM_CPUID_BIT_##x) >=20 > int kvm_update_cpuid(struct kvm_vcpu *vcpu) >@@ -392,7 +393,8 @@ static inline int __do_cpuid_ent(struct >kvm_cpuid_entry2 *entry, u32 function, >=20 > /* cpuid 7=2E0=2Eedx*/ > const u32 kvm_cpuid_7_0_edx_x86_features =3D >- KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS); >+ KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS) | \ >+ (boot_cpu_has(X86_FEATURE_SPEC_CTRL) ? KF(SPEC_CTRL) : 0); >=20 > /* all calls to cpuid_count() should be made on the same cpu */ > get_cpu(); >diff --git a/arch/x86/kvm/cpuid=2Eh b/arch/x86/kvm/cpuid=2Eh >index cdc70a3=2E=2Edcfe227 100644 >--- a/arch/x86/kvm/cpuid=2Eh >+++ b/arch/x86/kvm/cpuid=2Eh >@@ -54,6 +54,7 @@ static const struct cpuid_reg reverse_cpuid[] =3D { > [CPUID_8000_000A_EDX] =3D {0x8000000a, 0, CPUID_EDX}, > [CPUID_7_ECX] =3D { 7, 0, CPUID_ECX}, > [CPUID_8000_0007_EBX] =3D {0x80000007, 0, CPUID_EBX}, >+ [CPUID_7_EDX] =3D { 7, 0, CPUID_EDX}, > }; >=20 >static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned >x86_feature) >diff --git a/arch/x86/kvm/vmx=2Ec b/arch/x86/kvm/vmx=2Ec >index aa8638a=2E=2E1b743a0 100644 >--- a/arch/x86/kvm/vmx=2Ec >+++ b/arch/x86/kvm/vmx=2Ec >@@ -920,6 +920,9 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, >bool masked); > static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, > u16 error_code); > static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); >+static void __always_inline vmx_disable_intercept_for_msr(unsigned >long *msr_bitmap, >+ u32 msr, int type); >+ >=20 > static DEFINE_PER_CPU(struct vmcs *, vmxarea); > static DEFINE_PER_CPU(struct vmcs *, current_vmcs); >@@ -2007,6 +2010,28 @@ static void add_atomic_switch_msr(struct >vcpu_vmx *vmx, unsigned msr, > m->host[i]=2Evalue =3D host_val; > } >=20 >+/* do not touch guest_val and host_val if the msr is not found */ >+static int read_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, >+ u64 *guest_val, u64 *host_val) >+{ >+ unsigned i; >+ struct msr_autoload *m =3D &vmx->msr_autoload; >+ >+ for (i =3D 0; i < m->nr; ++i) >+ if (m->guest[i]=2Eindex =3D=3D msr) >+ break; >+ >+ if (i =3D=3D m->nr) >+ return 1; >+ >+ if (guest_val) >+ *guest_val =3D m->guest[i]=2Evalue; >+ if (host_val) >+ *host_val =3D m->host[i]=2Evalue; >+ >+ return 0; >+} >+ >static bool update_transition_efer(struct vcpu_vmx *vmx, int >efer_offset) > { > u64 guest_efer =3D vmx->vcpu=2Earch=2Eefer; >@@ -3203,7 +3228,9 @@ static inline bool >vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, > */ >static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data >*msr_info) > { >+ u64 spec_ctrl =3D 0; > struct shared_msr_entry *msr; >+ struct vcpu_vmx *vmx =3D to_vmx(vcpu); >=20 > switch (msr_info->index) { > #ifdef CONFIG_X86_64 >@@ -3223,6 +3250,19 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, >struct msr_data *msr_info) > case MSR_IA32_TSC: > msr_info->data =3D guest_read_tsc(vcpu); > break; >+ case MSR_IA32_SPEC_CTRL: >+ if (!msr_info->host_initiated && >+ !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) >+ return 1; >+ >+ /* >+ * If the MSR is not in the atomic list yet, then it was never >+ * written to=2E So the MSR value will be '0'=2E >+ */ >+ read_atomic_switch_msr(vmx, MSR_IA32_SPEC_CTRL, &spec_ctrl, NULL); >+ >+ msr_info->data =3D spec_ctrl; >+ break; > case MSR_IA32_SYSENTER_CS: > msr_info->data =3D vmcs_read32(GUEST_SYSENTER_CS); > break; >@@ -3289,6 +3329,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, >struct msr_data *msr_info) > int ret =3D 0; > u32 msr_index =3D msr_info->index; > u64 data =3D msr_info->data; >+ unsigned long *msr_bitmap; >+ >+ /* >+ * IBRS is not used (yet) to protect the host=2E Once it does, this >+ * variable needs to be a bit smarter=2E >+ */ >+ u64 host_spec_ctrl =3D 0; >=20 > switch (msr_index) { > case MSR_EFER: >@@ -3330,6 +3377,22 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, >struct msr_data *msr_info) > case MSR_IA32_TSC: > kvm_write_tsc(vcpu, msr_info); > break; >+ case MSR_IA32_SPEC_CTRL: >+ if (!msr_info->host_initiated && >+ !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) >+ return 1; >+ >+ /* >+ * Now we know that the guest is actually using the MSR, so >+ * atomically load and save the SPEC_CTRL MSR and pass it >+ * through to the guest=2E >+ */ >+ add_atomic_switch_msr(vmx, MSR_IA32_SPEC_CTRL, msr_info->data, >+ host_spec_ctrl); >+ msr_bitmap =3D vmx->vmcs01=2Emsr_bitmap; >+ vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); >+ >+ break; > case MSR_IA32_CR_PAT: > if (vmcs_config=2Evmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { > if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))