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From: Avi Kivity <avi@redhat.com>
To: Jon Mason <mason@myri.com>
Cc: Sven Schnelle <svens@stackframe.org>,
	Simon Kirby <sim@hostway.ca>,
	Eric Dumazet <eric.dumazet@gmail.com>,
	Niels Ole Salscheider <niels_ole@salscheider-online.de>,
	Jesse Barnes <jbarnes@virtuousgeek.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	Ben Hutchings <bhutchings@solarflare.com>
Subject: Re: Workaround for Intel MPS errata
Date: Tue, 04 Oct 2011 11:46:28 +0200	[thread overview]
Message-ID: <4E8AD5F4.7000201@redhat.com> (raw)
In-Reply-To: <20111003151158.GA21955@myri.com>

On 10/03/2011 05:12 PM, Jon Mason wrote:
>      PCI: Workaround for Intel MPS errata
>
>      Intel 5000 and 5100 series memory controllers have a known issue if read
>      completion coalescing is enabled (the default setting) and the PCI-E
>      Maximum Payload Size is set to 256B.  To work around this issue, disable
>      read completion coalescing if the MPS is 256B.
>
>      It is worth noting that there is no function to undo the disable of read
>      completion coalescing, and the performance benefit of read completion
>      coalescing will be lost if the MPS is set from 256B to 128B.  It is only
>      possible to have this issue via hotplug removing the only 256B MPS
>      device in the system (thus making all of the other devices in the system
>      have a performance degradation without the benefit of any 256B
>      transfers).  Therefore, this trade off is acceptable.
>
>      http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf
>      http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf
>
>      Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into
>      the problem.
>
>      Reported-by: Avi Kivity<avi@redhat.com>
>      Signed-off-by: Jon Mason<mason@myri.com>
>
> +
> +		if (!(val&  (1<<  10))) {
> +			done = true;
> +			return;
> +		}

Here, you bail out if bit 10 is clear.  So if we're here, it's set.

> +
> +		val |= (1<<  10);

Now it's even more set?

> +		err = pci_bus_write_config_word(bus, 0, 0x48, val);
> +		if (err) {
> +			dev_err(&bus->dev, "Error attempting to write the read "
> +				"completion coalescing register.\n");
> +			return;
> +		}
> +
> +		dev_info(&bus->dev, "Read completion coalescing disabled due "
> +			 "to hardware errata relating to 256B MPS.\n");
> +
> +		done = true;
> +	}
> +}
> +
>

-- 
error compiling committee.c: too many arguments to function


  reply	other threads:[~2011-10-04  9:46 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-09-27 17:01 [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" Avi Kivity
2011-09-27 17:59 ` Jon Mason
2011-09-27 18:28   ` Avi Kivity
2011-09-27 20:11     ` Jon Mason
2011-09-29  4:33       ` Benjamin Herrenschmidt
2011-09-29 13:53         ` Jon Mason
2011-09-30  0:16     ` Workaround for Intel MPS errata Jon Mason
2011-09-30  2:21       ` Jesse Brandeburg
2011-09-30  2:51         ` Jon Mason
2011-09-30  5:01       ` Bjorn Helgaas
2011-09-30 15:35         ` Jon Mason
2011-09-30 17:17           ` Bjorn Helgaas
2011-09-30 17:38             ` Jon Mason
2011-09-30 17:57               ` Bjorn Helgaas
2011-09-30  7:03       ` Rolf Eike Beer
2011-09-30 15:39         ` Jon Mason
2011-10-02  9:26       ` Avi Kivity
2011-10-03  4:58         ` Jon Mason
2011-10-03 10:11           ` Avi Kivity
2011-10-03 15:12             ` Jon Mason
2011-10-04  9:46               ` Avi Kivity [this message]
2011-10-04 13:06                 ` Avi Kivity
2011-10-04 13:11                   ` Jon Mason
2011-10-04 20:12                   ` Jon Mason
2011-10-05  3:46                   ` Jon Mason
2011-10-05 12:09                     ` Avi Kivity

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