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To: "Denis V. Lunev" , Jim Mattson , Konstantin Khorenko Cc: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231109180646.2963718-1-khorenko@virtuozzo.com> <09116ed9-3409-4fbf-9c4f-7a94d8f620aa@virtuozzo.com> Content-Language: en-US From: Dongli Zhang In-Reply-To: <09116ed9-3409-4fbf-9c4f-7a94d8f620aa@virtuozzo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BLAPR03CA0015.namprd03.prod.outlook.com (2603:10b6:208:32b::20) To BYAPR10MB2663.namprd10.prod.outlook.com (2603:10b6:a02:a9::20) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR10MB2663:EE_|PH7PR10MB6203:EE_ X-MS-Office365-Filtering-Correlation-Id: 69dd80ff-a5fe-43fb-2fb6-08dbe1803465 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 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X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-09_17,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311090177 X-Proofpoint-GUID: 686w3UjCO5QhA5DHqHNFUwp8Ul43E-xG X-Proofpoint-ORIG-GUID: 686w3UjCO5QhA5DHqHNFUwp8Ul43E-xG Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/9/23 3:46 PM, Denis V. Lunev wrote: > On 11/9/23 23:52, Jim Mattson wrote: >> On Thu, Nov 9, 2023 at 10:18 AM Konstantin Khorenko >> wrote: >>> Hi All, >>> >>> as a followup for my patch: i have noticed that >>> currently Intel kernel code provides an ability to detect if PMU is totally >>> disabled for a VM >>> (pmu->version == 0 in this case), but for AMD code pmu->version is never 0, >>> no matter if PMU is enabled or disabled for a VM (i mean >>> in the VM config which >>> results in "-cpu pmu=off" qemu option). >>> >>> So the question is - is it possible to enhance the code for AMD to also honor >>> PMU VM setting or it is >>> impossible by design? >> The AMD architectural specification prior to AMD PMU v2 does not allow >> one to describe a CPU (via CPUID or MSRs) that has fewer than 4 >> general purpose PMU counters. While AMD PMU v2 does allow one to >> describe such a CPU, legacy software that knows nothing of AMD PMU v2 >> can expect four counters regardless. >> >> Having said that, KVM does provide a per-VM capability for disabling >> the virtual PMU: KVM_CAP_PMU_CAPABILITY(KVM_PMU_CAP_DISABLE). See >> section 8.35 in Documentation/virt/kvm/api.rst. > But this means in particular that QEMU should immediately > use this KVM_PMU_CAP_DISABLE if this capability is supported and PMU=off. I am > not seeing this code thus I believe that we have missed this. I think that this > change worth adding. We will measure the impact :-) Den > I used to have a patch to use KVM_PMU_CAP_DISABLE in QEMU, but that did not draw many developers' attention. https://lore.kernel.org/qemu-devel/20230621013821.6874-2-dongli.zhang@oracle.com/ It is time to first re-send that again. Dongli Zhang