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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af635a62af3sm592795066b.84.2025.07.29.06.30.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Jul 2025 06:30:12 -0700 (PDT) Message-ID: <4a1c3cf1-9688-4275-87ac-8fffd4469889@oss.qualcomm.com> Date: Tue, 29 Jul 2025 15:30:10 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/17] drm/msm/a6xx: Switch to GMU AO counter To: rob.clark@oss.qualcomm.com Cc: Akhil P Oommen , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-9-9347aa5bcbd6@oss.qualcomm.com> <0a2188e7-3919-48f7-b5c1-8f779f617f28@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: f_DRG_C1kQkJ9FKJMmAoOoxK932M3XjJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI5MDEwNCBTYWx0ZWRfX3qsCc9M7xYU8 A9FB91SETM4w9DmFXoPbXbRr2BMWerrlPteVKKCMLYxtZFI2rzkYpgHcNF8Jukt1KMdP+IHBOPa zu9ZaKJMHZr110uUXSoIgjcksXE0tLebOaWTy0EJYNUNBoPcuaPHETuxO5IgJMh6TBZ9XpA5LRk XOf93kPaBkxT8nxWKlvV0T8GY1xLUgXXm2lJR/e1lWv6iFoF6ApJBSK8IXxh+JSN61FKxqrx/1h 4C3/Ge/c9BnETjPf4tYLccKxn3Sbdfd+1SO72d2G41ddBDvknISpExgehXiq3+yap2Bfmm1K9oc VubdY6umRJ5D75/xqMcD/+a9Eb56Loi+qIZau/5z4w7Vto6lZA6JS7zBq6HccdDWU/zgw891mwx +QEVkLIwvA8m0ZolvS4HQ/OAG7AIV7ciISCBvbT8OH/5CqDmc5DPrKVI0jW5hUfQrMjg/St+ X-Authority-Analysis: v=2.4 cv=HfYUTjE8 c=1 sm=1 tr=0 ts=6888cce7 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ERHQbKNnysnh4IVj_LEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: f_DRG_C1kQkJ9FKJMmAoOoxK932M3XjJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-29_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507290104 On 7/23/25 2:15 PM, Rob Clark wrote: > On Wed, Jul 23, 2025 at 3:19 AM Konrad Dybcio > wrote: >> >> On 7/20/25 2:16 PM, Akhil P Oommen wrote: >>> CP_ALWAYS_ON counter falls under GX domain which is collapsed during >>> IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is >>> not impacted by IFPC. Both counters are clocked by same xo clock source. >>> >>> Signed-off-by: Akhil P Oommen >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++++++-------------- >>> 1 file changed, 16 insertions(+), 14 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> index 6770f0363e7284e4596b1188637a4615d2c0779b..f000915a4c2698a85b45bd3c92e590f14999d10d 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> @@ -16,6 +16,19 @@ >>> >>> #define GPU_PAS_ID 13 >>> >>> +static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu) >>> +{ >>> + u64 count_hi, count_lo, temp; >>> + >>> + do { >>> + count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); >>> + count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); >>> + temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); >>> + } while (count_hi != temp); >> >> The original logic is as follows: >> >> static u64 gen7_read_alwayson(struct adreno_device *adreno_dev) >> { >> struct kgsl_device *device = KGSL_DEVICE(adreno_dev); >> u32 lo = 0, hi = 0, tmp = 0; >> >> /* Always use the GMU AO counter when doing a AHB read */ >> gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_H, &hi); >> gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_L, &lo); >> >> /* Check for overflow */ >> gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_H, &tmp); >> >> if (hi != tmp) { >> gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_L, >> &lo); >> hi = tmp; >> } >> >> return (((u64) hi) << 32) | lo; >> } >> >> Doing this in a while-loop almost looks like you want a lot of time to >> pass - REG_WIDTH(u32?)/19.2 MHz > > would: > > } while (unlikely(count_hi != temp)); > > make it more clear? I guess so Konrad