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Sat, 14 Nov 2026 08:29:17 -0800 (PST) Received: from [192.168.1.12] ([122.164.84.214]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-379569b8389sm30930509eec.25.2026.11.14.08.29.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Nov 2026 08:29:16 -0800 (PST) Message-ID: <4a2b0d2a-129b-452e-84d1-dad83353b10f@oss.qualcomm.com> Date: Sat, 14 Nov 2026 21:59:09 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/11] dt-bindings: clock: qcom: ipq5332-gcc: Describe clock inputs per compatible To: Krzysztof Kozlowski , Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Konrad Dybcio , Dmitry Baryshkov , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org References: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> <20260921-ipq_clk_changes-v1-5-d242e3d49648@oss.qualcomm.com> <62a5fabc-3a06-42fa-9c6b-6504650e712b@kernel.org> <7bcffc7c-5dda-4ead-a053-7eb4980e43a4@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: H3k3xZ2Nsb2xuTo_L_yUcxb3hORPzWAs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTE0MDA2NSBTYWx0ZWRfX2MYRVXFPV+Qv Ji3mS82WQLkuyxDuRrRXhbJgiuSxzfvR17pUxlufrnzi8lDTI71lSs/nxrURLUQ2UXq79xp/sdk lC9NT+7fvLtEuVt0GhhmjBBOVUHZVCbgctvPY+qtoXnk9tynizvwZA2rpiKdN7APeceTm8/p3jW 9Lxye2GD9LXiC8ezp5j659EIkhsfLD5p0Y295BCUDQITRVfRmlHEdlTLAa7mVzmhYQfM9de+dox KpBpz/qkwMtjiUNgbxrhc/jGpfkFNZmlIWPwRK2lFDSBrUmHnlabNAghM4Je75TwcyKXvwTBODg uO8HwPROFFSgeCvohjAsSNwsy/Bvd+vBBQEIbsqRS9AczlFt1I6Z5u1JjKOf/ssh4cwuHuDjwQT SuGokKOTuyPLXzy7GyBAh3Lh7WWZWcX9zZ0ZIB3djO4u/EwRCm/PC8aSZjkkrvmJZclttqkQVm4 knY+Xks7FHQV5qRJ3iA== X-Authority-Analysis: v=2.4 cv=NdhzRGD4 c=1 sm=1 tr=0 ts=6af88c5f cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=cs/8+e8xk1Wfje/1H545Gg==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Mw7ywA0MMAP2sS5nzLUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: H3k3xZ2Nsb2xuTo_L_yUcxb3hORPzWAs X-Proofpoint-Spam-Info: AW1haW4tMjYxMTE0MDA2NSBTYWx0ZWRfX4a4oHlAxOATY VDIOP+Sf9qFQTLnr86rN+ZsP2GxPlx9i1GCuBeY8OZV4br8RZcFHXKWGoCZElzwPyls9XTZOapf tp8ZJ0WB2pRg0tNZDurBV0LaXpESrNI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-14_04,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611140065 On 11/12/2026 3:02 PM, Krzysztof Kozlowski wrote: > On 12/11/2026 10:12, Kathiravan Thirumoorthy wrote: >> On 9/25/2026 12:09 PM, Kathiravan Thirumoorthy wrote: >>> On 9/24/2026 4:28 PM, Krzysztof Kozlowski wrote: >>>> On 24/09/2026 11:15, Kathiravan Thirumoorthy wrote: >>>>> On 9/23/2026 2:17 PM, Krzysztof Kozlowski wrote: >>>>>> On 21/09/2026 08:19, Kathiravan Thirumoorthy wrote: >>>>>>> The IPQ5332 and IPQ5424 GCC blocks use different clock input >>>>>>> orderings. >>>>>>> Document the clock inputs in compatible-specific schema >>>>>>> constraints instead >>>>>>> of using a common clock description. >>>>>>> >>>>>>> Also add the 375 MHz PPE clock generated by the CMN PLL to the >>>>>>> IPQ5424 >>>>>>> clock input list. >>>>>>> >>>>>>> This keeps the binding aligned with the clock ordering used by the >>>>>>> existing DTS and GCC driver implementations. >>>>>>> >>>>>>> Signed-off-by: Kathiravan Thirumoorthy >>>>>>> >>>>>>> --- >>>>>>>    .../bindings/clock/qcom,ipq5332-gcc.yaml           | 26 >>>>>>> +++++++++++++--------- >>>>>>>    1 file changed, 16 insertions(+), 10 deletions(-) >>>>>>> >>>>>>> diff --git >>>>>>> a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>>>>> b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>>>>> index 1230183fc0a9..fb39dffca988 100644 >>>>>>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>>>>> @@ -25,14 +25,7 @@ properties: >>>>>>>         clocks: >>>>>>>        minItems: 5 >>>>>>> -    items: >>>>>>> -      - description: Board XO clock source >>>>>>> -      - description: Sleep clock source >>>>>>> -      - description: PCIE 2lane PHY pipe clock source >>>>>>> -      - description: PCIE 2lane x1 PHY pipe clock source (For >>>>>>> second lane) >>>>>>> -      - description: USB PCIE wrapper pipe clock source >>>>>>> -      - description: PCIE 2-lane PHY2 pipe clock source >>>>>>> -      - description: PCIE 2-lane PHY3 pipe clock source >>>>>> You are changing the order which is ABI break. Describe the actual >>>>>> problem to justify such change. Are you saying this was broken since >>>>>> beginning or what exactly is not working here? The driver was added by >>>>>> Qualcomm in 2024, so how did it even work? It's not some 10 yo legacy >>>>>> where we did some mistakes in binding while converting from TXT. >>>>>> >>>>>> Also, I do not get why the list cannot be shared. >>>>> When the bindings was posted, list is combined for both IPQ5332 and >>>>> IPQ5424. But the driver wasn't updated and it was following the below >>>>> order, so was DTS, which is not compatible the DT binding description. >>>>> >>>>> enum { >>>>>           DT_XO, >>>>>           DT_SLEEP_CLK, >>>>>           DT_PCIE30_PHY0_PIPE_CLK, >>>>>           DT_PCIE30_PHY1_PIPE_CLK, >>>>>           DT_PCIE30_PHY2_PIPE_CLK, >>>>>           DT_PCIE30_PHY3_PIPE_CLK, >>>>>           DT_USB_PCIE_WRAPPER_PIPE_CLK, >>>>>           DT_CMN_PLL_NSS_375M_CLK, >>>>> }; >>>>> >>>>> So I'm splitting the description between IPQ5332 and IPQ5424 to >>>>> matching >>>>> with the DTS and the driver description. >>>> So we asked back in 2024 to have the common part of the list. I even did >>>> the effort to dig it: >>>> >>>> https://lore.kernel.org/all/ruti7hmkxkayzmqfbme6rw6j2vbhlx4ul4ptcckwamcpd4cyfx@owufhxwpvlcj/ >>>> >>>> >>>> Authors implemented it partially, broken drivers. Now you basically >>>> revert what we asked, which is BTW logical option. It's logical and >>>> reasonable, but leaves bitter feeling. >>>> >>>> I have feeling there is no accountability and no responsibility of the >>>> IPQ at all. >>>> >>>> No, that's not going to work. You cannot come 1.5 year later and revert >>>> what reviewer asked you, even if issue was just by mistake in the first >>>> place. And you should not even try to do that. >>> I understand the concern, and I agree this should have been caught much >>> earlier. >>> >>> I only discovered the mismatch while working on the IPQ5424 clock >>> additions. My intent here is resolve the inconsistency that currently >>> exists between the binding and implementation. >>> >>>> NAK >>> I'm happy to explore an alternative approach if updating the binding is >>> not considered acceptable. >> Krzysztof, I understand the frustration behind this, and we will make >> sure issues like this are caught earlier going forward. >> >> Could you please advise us on the acceptable way forward for this series? >> > Unfortunately I don't know what to advise. I cannot Ack it, because > people look at history commits, take them out of context and use as > arguments in discussion ("oh look, here you acked such change, so I can > do the same"). > > Maintainer's feedback was basically only partially implemented and now > you want to revert that part which was implemented, basically opening > the gate to allow such patterns in the future. I don't know how you are > going to guarantee such issues will not happen in the future, so I guess > you need to live with broken platform. Please align with Qualcomm SoC > maintainers on this, because I will not ack it. Bjorn, could you please share your thoughts on this and suggest how we should proceed? These clocks are required by the networking modules. Patches 11 and 12 are independent of this discussion. Since resolving this may take some time, would it make sense for me to send those separately so they can move forward independently? > > Best regards, > Krzysztof