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Fri, 26 Sep 2025 06:39:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGiaP1HxRLVUpY8VZEiq5l3q06EZMQQVXQhWmy8UEaYDj2MmG+Nz3UAs4qURBGWNpupm3mF0Q== X-Received: by 2002:a05:6a00:23cc:b0:780:f6db:b1bd with SMTP id d2e1a72fcca58-780fcdd28d1mr8678917b3a.4.1758893967264; Fri, 26 Sep 2025 06:39:27 -0700 (PDT) Received: from [192.168.29.113] ([49.43.224.88]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-78102c048fasm4502469b3a.75.2025.09.26.06.39.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Sep 2025 06:39:26 -0700 (PDT) Message-ID: <4a3f9494-27a2-47d6-bdef-0b1bcbd99903@oss.qualcomm.com> Date: Fri, 26 Sep 2025 19:09:17 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 5/9] PCI: dwc: Implement .start_link(), .stop_link() hooks To: Bjorn Helgaas , Manivannan Sadhasivam Cc: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Catalin Marinas , Will Deacon , quic_vbadigan@quicnic.com, amitk@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov References: <20250925172517.GA2169496@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250925172517.GA2169496@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: DhIdM54dHMLPel2c_BDpLy2Jm0J84rhW X-Authority-Analysis: v=2.4 cv=JKA2csKb c=1 sm=1 tr=0 ts=68d69790 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=w+9hNF1SH6wH5mqaHp+xkw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=AYVm423qkfQxZcs1cpAA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: DhIdM54dHMLPel2c_BDpLy2Jm0J84rhW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI2MDA4OSBTYWx0ZWRfXzFEnkQjajQq3 iaGYKLWsch9K5rbMUX3/Y2TotimAxOQnUXRXj6FKlPLVAxu+5quG4I3T0nNCyXPSOURvMpfqH+K G2ptq8TQxNn3sxcivMgyZMDhxvv5/MRAYZBRF0ApzuwC9UvQv8E2d4ENV5b+eLL4+YptKqhCAWB 29GgLfLEdfoMTGgjG9kMKkJvhZlqWzxe6KBGXIkOqCo+p/33ptYqT02e8eBZ4hVUMc3NA1o2UGi 4ClsdBric8bL9aGoSteNPnzVqT+bglmBSom4/G+X6qMJ5RyiDi3WZkuX3qojKjQUMJVJUrS4aaK 0XYf0D8GvNsZYq/CKgc08m9NeDm081k++u7Dn4c5mxa98davv5PBCyXa+5rxLi0bUpIGZ38V/U5 Tc+yyVPtlAOwSbFrcDa50F8WAiIDKw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-26_04,2025-09-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509260089 On 9/25/2025 10:55 PM, Bjorn Helgaas wrote: > On Thu, Sep 25, 2025 at 09:49:16PM +0530, Manivannan Sadhasivam wrote: >> On Thu, Sep 25, 2025 at 09:54:16AM -0500, Bjorn Helgaas wrote: >>> On Thu, Aug 28, 2025 at 05:39:02PM +0530, Krishna Chaitanya Chundru wrote: >>>> Implement stop_link() and start_link() function op for dwc drivers. >>>> >>>> Signed-off-by: Krishna Chaitanya Chundru >>>> --- >>>> drivers/pci/controller/dwc/pcie-designware-host.c | 18 ++++++++++++++++++ >>>> 1 file changed, 18 insertions(+) >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> index 952f8594b501254d2b2de5d5e056e16d2aa8d4b7..bcdc4a0e4b4747f2d62e1b67bc1aeda16e35acdd 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >>>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> @@ -722,10 +722,28 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, >>>> } >>>> EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); >>>> >>>> +static int dw_pcie_op_start_link(struct pci_bus *bus) >>>> +{ >>>> + struct dw_pcie_rp *pp = bus->sysdata; >>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >>>> + >>>> + return dw_pcie_host_start_link(pci); >>> >>> This takes a pci_bus *, which could be any PCI bus, but this only >>> works for root buses because it affects the link from a Root Port. >>> >>> I know the TC9563 is directly below the Root Port in the current >>> topology, but it seems like the ability to configure a Switch with >>> I2C or similar is potentially of general interest, even if the >>> switch is deeper in the hierarchy. >>> >>> Is there a generic way to inhibit link training, e.g., with the >>> Link Disable bit in the Link Control register? If so, this could >>> potentially be done in a way that would work for any vendor and >>> for any Downstream Port, including Root Ports and Switch >>> Downstream Ports. >> >> FWIW, the link should not be stopped for a single device, since it >> could affect other devices in the bus. Imagine if this switch is >> connected to one of the downstream port of another switch. Then >> stopping and starting the link will affect other devices connected >> to the upstream switch as well. > > Link Disable would affect all devices downstream of the bridge where > it is set, same as dw_pcie_op_stop_link(). > >> This driver is doing it right now just because, there is no other >> way to control the switch state machine. Ideally, we would want the >> PERST# to be in asserted stage to keep the device from starting the >> state machine, then program the registers over I2C and deassert >> PERST#. This will work across all of the host controller drivers (if >> they support pwrctrl framework). > > I don't think there's a way to implement .start_link() and > .stop_link() for ACPI unless it's by using Link Disable, which is why > I asked about this. If Link Disable *does* work, it would be a very > generic way to do this because it's part of the PCIe base spec. > Hi Bjorn, We did test as you suggested but unfortunately the setting are not getting reflected we need to explicitly assert perst to make sure pcie is in reset state while applying these settings. - Krishna Chaitanya. > Bjorn >