From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC4ECC433E6 for ; Thu, 21 Jan 2021 10:48:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B54A2395B for ; Thu, 21 Jan 2021 10:48:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729849AbhAUKsM (ORCPT ); Thu, 21 Jan 2021 05:48:12 -0500 Received: from mail.kernel.org ([198.145.29.99]:34274 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729698AbhAUKiL (ORCPT ); Thu, 21 Jan 2021 05:38:11 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7DE5F2137B; Thu, 21 Jan 2021 10:37:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611225450; bh=1Etgxdl7G90TmACNnd/HP+WyqVm5tYgY7rcqWBkqz1o=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=L3pYFv9W108WGMDPWi2nQT4KorANRg8DC1BzTytUbdgR4M6NlMNlffrcpWdcPuIW3 EzEUQw2KV/ujhqu2GBookYeDWnnnFUZG8JbgYM5AqlBsUdsXMYsIKp9uuvpN9/UdvW qEex+BXxq4+C8/6g+nbXeiSvuPCjYEr6g0tvTspjSKpyL12T+EXdZS+tloCa2GwWeF vWImlQp+bye98LMj682xhVUxPMuGGKh0iNkSVrQ6rmBXeztFqwU5I69lZEZE7iNNRv fPBI//Ul0nam2uf+jXOHEAJDseh7PQ4IbVNnaNJttoRaDoJGOQTxxKzeoCU/lVNoQo EijkIVLoHZd/w== Subject: Re: [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific To: Nishanth Menon , Sudeep Holla , Suman Anna , Dave Gerlach Cc: Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20210120195145.32259-1-nm@ti.com> From: Tero Kristo Message-ID: <4a57ef04-75ca-5d24-54ef-15aff1ede46e@kernel.org> Date: Thu, 21 Jan 2021 12:37:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210120195145.32259-1-nm@ti.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/01/2021 21:51, Nishanth Menon wrote: > We can use CPU specific pmu configuration to expose the appropriate > CPU specific events rather than just the basic generic pmuv3 perf > events. > > Reported-by: Sudeep Holla > Signed-off-by: Nishanth Menon Reviewed-by: Tero Kristo > --- > > AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/ > J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/ > J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/ > > Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/ > > I have'nt split this patch up for fixes tag primarily because the > basic functionality works and this is an improvement than a critical > fixup to backport for older kernels. > > arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +- > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- > arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi > index d84c0bc05023..a9fc1af03f27 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi > @@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 { > }; > > pmu: pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > /* Recommendation from GIC500 TRM Table A.3 */ > interrupts = ; > }; > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > index 66169bcf7c9a..b7005b803149 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > @@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 { > }; > > pmu: pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a72-pmu"; > interrupts = ; > }; > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi > index cc483f7344af..f0587fde147e 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi > @@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 { > }; > > pmu: pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a72-pmu"; > /* Recommendation from GIC500 TRM Table A.3 */ > interrupts = ; > }; >