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Mon, 12 Jan 2026 02:26:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IGI6qx3J+uQ+5qvS5B0ynvsIyZCgYZuZrZmLW2dtC/5Po5VbaT72bNm4abYOxU/5lW7PXjRKg== X-Received: by 2002:aa7:80d7:0:b0:81c:96b7:7fa7 with SMTP id d2e1a72fcca58-81c96b791bfmr10082793b3a.42.1768213579015; Mon, 12 Jan 2026 02:26:19 -0800 (PST) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-81e7fd708fdsm8531052b3a.65.2026.01.12.02.26.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Jan 2026 02:26:18 -0800 (PST) Message-ID: <4ab4cf95-6ccc-4eb8-82d3-78ebb6e7930f@oss.qualcomm.com> Date: Mon, 12 Jan 2026 15:56:14 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source To: Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260112-dp-aux-clks-v1-0-456b0c11b069@oss.qualcomm.com> <20260112-dp-aux-clks-v1-2-456b0c11b069@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20260112-dp-aux-clks-v1-2-456b0c11b069@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: nzzjICVho0wMSjTutTANnyHT6jBMwL_Q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA4MiBTYWx0ZWRfX32vEwuH1NsC6 r2SA6Y+KgMwbfNu3HNCWfo3vjLzk0Ayrcv7T+RWE42HACb4tpjT2tCkN0PhtnNNgFVY2x8yYpPV ubJBOe4uTL2M6SUoM4i5CVit4jYF+pu6fkYX50hDZqDU5hFCf71JX7YQ1Lm30mnPNN61JwROglx YE8MpixqlLNspryCWWzEIWiZdgw2OrwdY1Sh8hdepxHb6fldCrWWbOdawztGLKkjzfxieUKPVZ0 c6ulol+79n2fX4nW3NqMdw27wSsJ4GbeCeb/Fy6XsR5MoAqqK91LxqGjcmyLaGsGCLlAon1Sk+N q8zX9n69uublK8rqtvV9QgBdCuuRXbeDFhR/FEFvwJWEfpZCK5ooyp16NYtxlEOcDZiAm3bXOzc vt78OBLjYG3rYJC03s8oU74rCdLx6ilRYe9qchr3Yc+szNLPAgZIAdI5RX90TS+4Fyr2IOlqlhu l/p+PLoMzsqrNTa6fxA== X-Proofpoint-ORIG-GUID: nzzjICVho0wMSjTutTANnyHT6jBMwL_Q X-Authority-Analysis: v=2.4 cv=EovfbCcA c=1 sm=1 tr=0 ts=6964cc4c cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=FCWHNvtYXcGM2Pe_cTUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_03,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120082 On 1/12/2026 7:42 AM, Dmitry Baryshkov wrote: > The clk_dp_ops are supposed to be used for DP-related clocks with a > proper MND divier. Use standard RCG2 ops for dptx1_aux_clk_src, the same > as all other DPTX AUX clocks in this driver. > > Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/dispcc-sm8450.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c > index 9ce9fd28e55b..2e91332dd92a 100644 > --- a/drivers/clk/qcom/dispcc-sm8450.c > +++ b/drivers/clk/qcom/dispcc-sm8450.c > @@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_dp_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > Reviewed-by: Taniya Das -- Thanks, Taniya Das