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Mon, 01 Jun 2026 01:30:01 -0700 (PDT) X-Received: by 2002:a17:90b:5101:b0:36b:7c4e:1b07 with SMTP id 98e67ed59e1d1-36c4feeb84emr11044975a91.5.1780302601467; Mon, 01 Jun 2026 01:30:01 -0700 (PDT) Received: from [10.217.216.23] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36bbdd1a855sm4491346a91.6.2026.06.01.01.29.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jun 2026 01:30:00 -0700 (PDT) Message-ID: <4ab6aa28-6b0b-436f-95d3-23b54d73a992@oss.qualcomm.com> Date: Mon, 1 Jun 2026 13:59:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/9] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled To: Bryan O'Donoghue , Erikas Bitovtas , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Andr=C3=A9_Apitzsch?= , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Brian Masney Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org References: <20260519-msm8939-venus-rfc-v8-0-542ec7557ebc@gmail.com> <20260519-msm8939-venus-rfc-v8-2-542ec7557ebc@gmail.com> <608dc53d-17a8-4230-9ebb-48a94bf03675@kernel.org> <6ae3a89c-f205-45c5-87c0-5550f78502d6@oss.qualcomm.com> <01f9a303-846a-4048-8115-c94b9b78078a@gmail.com> <4JzpVyRt008YHZIv34VGG-Z_etL_fh9cE8AL30d-uekLUAxGmZNV9os6xkESzPAyzDHFHA9XXyPgWxzBlEfnhQ==@protonmail.internalid> <82f7a200-ab07-4ff4-b84e-305351f78460@kernel.org> Content-Language: en-US From: Taniya Das In-Reply-To: <82f7a200-ab07-4ff4-b84e-305351f78460@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: ChBWBRBc7Wn4EatyMjVW0_QLcPizLGYn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAxMDA4NCBTYWx0ZWRfX1OHBVTMfyzVf VZxZlTx9tqzdPx4t76DlJw+gKQUU8kAOL4i+kmIqLcLCHj+toguF2AmzvzcZM6xd1Y3CJ2cY4k1 ilj1taNSpzT8y1QW9x+yN82SuTq8lk+bgp6PcJhjSdTt9rurKL6OfkMr9UeR1JY2ly4HB+0WiGu 5fdjR4FHVGTngo3ZmwL851VGEiGGgSB+lsfbPLuNDvlmoDAd/opMRfhAufTOhAyfhZ7cGC4ayX1 AtB6/WF7PFknTDK/oa2KGoEaJSmY+o4BXA4NkNvb9Ux80tD93tDCwVg3wublL1NOQJEZCltH21q mRv362Usyt8TrBQbhg8KpPBfRkxo2VJDvZyO83rOdxuv65Lg343sTFF8Z6ID9FBv10CHnaxHSxS uD72O1gHWL6Lz7wOXHlGygGt82IRlUH3W7q8E6QfEkBtWn9bVBoO6/bBJOIL2C/jHzwWhleoXsA kosmYwOcaPtuXnYzfNg== X-Authority-Analysis: v=2.4 cv=NvvhtcdJ c=1 sm=1 tr=0 ts=6a1d430b cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=uEUO8UhmWA4g_SfyP1oA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: ChBWBRBc7Wn4EatyMjVW0_QLcPizLGYn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606010084 On 5/26/2026 4:20 AM, Bryan O'Donoghue wrote: > On 25/05/2026 10:56, Erikas Bitovtas wrote: >> +    for (; i < res->vcodec_pmdomains_num; i++) { >> +        pd_dev = core->pmdomains->pd_devs[i]; >> +        ret = pm_runtime_resume_and_get(pd_dev); >> +        if (ret) >> +            goto err; >> + >> +        ret = dev_pm_genpd_set_hwmode(pd_dev, true); >> +        if (ret && ret != -EOPNOTSUPP) { >> +            pm_runtime_put_sync(pd_dev); >> +            goto err; >> +        } >> +    } > > In Iris we do > > - enable_power_domains > - enable_clocks > - set hwmode > This sequence will always ensure clock can be polled as the GDSC is still in SW mode. > Instead of > > - enable_power_domains > - set hwmode > - enable clocks > This sequence will require the clock to have SKIP or DELAY as the GDSC is moved to HW mode and it is not guaranteed to match the SW expectation. -- Thanks, Taniya Das