From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Komal Bajaj <komal.bajaj@oss.qualcomm.com>,
Bartosz Golaszewski <brgl@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Linus Walleij <linusw@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pinctrl: qcom: shikra: Fix intr_target_width for summary interrupt routing
Date: Tue, 28 Jul 2026 13:09:57 +0200 [thread overview]
Message-ID: <4ac04a13-c2e8-43f6-a7cd-8f113803de41@oss.qualcomm.com> (raw)
In-Reply-To: <20260728-shikra-pinctrl-intr-width-v1-1-46583734d808@oss.qualcomm.com>
On 7/28/26 1:03 PM, Komal Bajaj wrote:
> The intr_target_width field sets the mask width used when writing
> target processor into interrupt config register and deciding which
> processor receives summary interrupt for a given GPIO.
>
> Without it, pinctrl driver defaults to a 3-bit mask. On Shikra, this
> field is 4 bits wide, which could corrupt adjacent bits and mis-route
> interrupts. Set intr_target_width = 4 to match the hardware.
>
> Fixes: 9db68ec534c5 ("pinctrl: qcom: Add Shikra pinctrl driver")
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
next prev parent reply other threads:[~2026-07-28 11:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 11:03 Komal Bajaj
2026-07-28 11:09 ` Konrad Dybcio [this message]
2026-07-31 8:31 ` Bartosz Golaszewski
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