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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id q11-20020adff94b000000b0033e95bf4796sm7905988wrr.27.2024.03.13.04.11.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Mar 2024 04:11:27 -0700 (PDT) Message-ID: <4ac22b8b-9230-4489-8b38-a2ba79c16d16@linaro.org> Date: Wed, 13 Mar 2024 12:11:26 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] clocksource: timer-riscv: Clear timer interrupt on timer initialization Content-Language: en-US To: Ley Foon Tan , Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: atishp@rivosinc.com, Samuel Holland , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ley Foon Tan , stable@vger.kernel.org References: <20240306172330.255844-1-leyfoon.tan@starfivetech.com> From: Daniel Lezcano In-Reply-To: <20240306172330.255844-1-leyfoon.tan@starfivetech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 06/03/2024 18:23, Ley Foon Tan wrote: > In the RISC-V specification, the stimecmp register doesn't have a default > value. To prevent the timer interrupt from being triggered during timer > initialization, clear the timer interrupt by writing stimecmp with a > maximum value. > > Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") > Cc: > Signed-off-by: Ley Foon Tan > > --- Applied, thanks -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog