From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B96871547EE for ; Thu, 11 Sep 2025 05:50:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757569815; cv=none; b=a80lBlnOb1EtRB08vHKQ1MiI3KIoD3iXW8Z75uzQnKWuESc8jCfu8F3pvHzseg66ktMdf/rCa4fwcAiv04RuR4SQ0ell3JJ4MP+S71U97JYUhzRdcFwbLpkxcWOC9UjWrT5YQepmKCGHm1Sq0WFtkg/bCcT/WKKdABP34HgLD38= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757569815; c=relaxed/simple; bh=I2JQ/iMHxzXpoaeWuxPGIGUa70P6xNp35enu4g6kd98=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ZYyyhB8J+hgH6/xJ4/axo+e5ET5Dlmlpr6j53TJqO+Ri3DHBFAScbFI2C1yalmtrA2x/Issb80bmyaQMKYGHrPIvedlazfnbhK8/tYvIV+GhT0lo0zr+KWwmmEc0Hvek13+pnZ36wjw1qD0nxW57tDfH9iNRzltzsGXbYR7uE6A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0CE2153B; Wed, 10 Sep 2025 22:50:04 -0700 (PDT) Received: from [10.164.18.53] (unknown [10.164.18.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F6FC3F694; Wed, 10 Sep 2025 22:50:10 -0700 (PDT) Message-ID: <4ac449f1-d5cc-42d6-bded-2db6984d55f0@arm.com> Date: Thu, 11 Sep 2025 11:20:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v1 1/2] arm64: tlbflush: Move invocation of __flush_tlb_range_op() to a macro To: Ryan Roberts , Catalin Marinas , Will Deacon , Mark Rutland , James Morse Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250829153510.2401161-1-ryan.roberts@arm.com> <20250829153510.2401161-2-ryan.roberts@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20250829153510.2401161-2-ryan.roberts@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 29/08/25 9:05 PM, Ryan Roberts wrote: > __flush_tlb_range_op() is a pre-processor macro that takes the TLBI > operation as a string, and builds the instruction from it. This prevents > passing the TLBI operation around as a variable. __flush_tlb_range_op() > also takes 7 other arguments. > > Adding extra invocations for different TLB operations means duplicating > the whole thing, but those 7 extra arguments are the same each time. > > Add an enum for the TLBI operations that __flush_tlb_range() uses, and a > macro to pass the operation name as a string to __flush_tlb_range_op(), > and the rest of the arguments using __VA_ARGS_. > > The result is easier to add new TLBI operations to, and to modify any of > the other arguments as they only appear once. > > Suggested-by: James Morse > Signed-off-by: Ryan Roberts > --- > arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index 18a5dc0c9a54..f66b8c4696d0 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -11,6 +11,7 @@ > #ifndef __ASSEMBLY__ > > #include > +#include > #include > #include > #include > @@ -433,12 +434,32 @@ static inline bool __flush_tlb_range_limit_excess(unsigned long start, > return false; > } > > +enum tlbi_op { > + TLBI_VALE1IS, > + TLBI_VAE1IS, > +}; > + > +#define flush_tlb_range_op(op, ...) \ > +do { \ > + switch (op) { \ > + case TLBI_VALE1IS: \ > + __flush_tlb_range_op(vale1is, __VA_ARGS__); \ > + break; \ > + case TLBI_VAE1IS: \ > + __flush_tlb_range_op(vae1is, __VA_ARGS__); \ > + break; \ > + default: \ > + BUILD_BUG_ON_MSG(1, "Unknown TLBI op"); \ > + } \ > +} while (0) > + > static inline void __flush_tlb_range_nosync(struct mm_struct *mm, > unsigned long start, unsigned long end, > unsigned long stride, bool last_level, > int tlb_level) > { > unsigned long asid, pages; > + enum tlbi_op tlbi_op; > > start = round_down(start, stride); > end = round_up(end, stride); > @@ -452,12 +473,9 @@ static inline void __flush_tlb_range_nosync(struct mm_struct *mm, > dsb(ishst); > asid = ASID(mm); > > - if (last_level) > - __flush_tlb_range_op(vale1is, start, pages, stride, asid, > - tlb_level, true, lpa2_is_enabled()); > - else > - __flush_tlb_range_op(vae1is, start, pages, stride, asid, > - tlb_level, true, lpa2_is_enabled()); > + tlbi_op = last_level ? TLBI_VALE1IS : TLBI_VAE1IS; > + flush_tlb_range_op(tlbi_op, start, pages, stride, asid, tlb_level, > + true, lpa2_is_enabled()); > > mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, end); > } Should the remaining __flush_tlb_range_op() in flush_tlb_kernel_range() converted into flush_tlb_range_op() adding another similar enum variable i.e TLBI_VAALE1IS ? Because this will ensure that there is one variant helper i.e flush_tlb_range_op() that gets called. diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index f66b8c4696d0..a23169751deb 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -437,6 +437,7 @@ static inline bool __flush_tlb_range_limit_excess(unsigned long start, enum tlbi_op { TLBI_VALE1IS, TLBI_VAE1IS, + TLBI_VAALE1IS, }; #define flush_tlb_range_op(op, ...) \ @@ -448,6 +449,9 @@ do { \ case TLBI_VAE1IS: \ __flush_tlb_range_op(vae1is, __VA_ARGS__); \ break; \ + case TLBI_VAALE1IS: \ + __flush_tlb_range_op(vaale1is, __VA_ARGS__); \ + break; \ default: \ BUILD_BUG_ON_MSG(1, "Unknown TLBI op"); \ } \ @@ -517,7 +521,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end } dsb(ishst); - __flush_tlb_range_op(vaale1is, start, pages, stride, 0, + flush_tlb_range_op(TLBI_VAALE1IS, start, pages, stride, 0, TLBI_TTL_UNKNOWN, false, lpa2_is_enabled()); dsb(ish); isb();