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Thu, 10 Oct 2024 14:36:04 +0200 (CEST) Message-ID: <4ac4c8ab-4180-4fcc-9e48-6dede7448dee@collabora.com> Date: Thu, 10 Oct 2024 14:36:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/4] arm64: dts: mediatek: mt7988: add pinctrl support To: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Sean Wang Cc: Frank Wunderlich , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, daniel@makrotopia.org, john@phrozen.org, ansuelsmth@gmail.com, eladwf@gmail.com References: <20241009165222.5670-1-linux@fw-web.de> <20241009165222.5670-5-linux@fw-web.de> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20241009165222.5670-5-linux@fw-web.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 09/10/24 18:52, Frank Wunderlich ha scritto: > From: Frank Wunderlich > > Add mt7988a pinctrl node. > > Signed-off-by: Frank Wunderlich > --- > v2: > - fix wrong alignment of reg values > --- > arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 241 ++++++++++++++++++++++ > 1 file changed, 241 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi > index c9649b815276..7e15934efe0b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi > @@ -3,6 +3,7 @@ > #include > #include > #include > +#include > > / { > compatible = "mediatek,mt7988a"; > @@ -105,6 +106,246 @@ clock-controller@1001e000 { > #clock-cells = <1>; > }; > > + pio: pinctrl@1001f000 { > + compatible = "mediatek,mt7988-pinctrl"; > + reg = <0 0x1001f000 0 0x1000>, > + <0 0x11c10000 0 0x1000>, > + <0 0x11d00000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11e00000 0 0x1000>, > + <0 0x11f00000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_tr", > + "iocfg_br", "iocfg_rb", > + "iocfg_lb", "iocfg_tl", "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 84>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; > + #interrupt-cells = <2>; > + > + mdio0_pins: mdio0-pins { > + mux { > + function = "eth"; > + groups = "mdc_mdio0"; > + }; > + > + conf { > + pins = "SMI_0_MDC", "SMI_0_MDIO"; > + drive-strength = ; Please do *not* use the MTK_DRIVE_(x)mA definitions anymore. Here it is `drive-strength = <8>`. > + }; > + }; > + > + i2c0_pins: i2c0-g0-pins { > + mux { > + function = "i2c"; > + groups = "i2c0_1"; > + }; > + }; > + > + i2c1_pins: i2c1-g0-pins { > + mux { > + function = "i2c"; > + groups = "i2c1_0"; > + }; > + }; Whatever pin can be configured with one or multiple groups that can be different must *not* be in the SoC dtsi, but rather in the *board* dts(i) file, as the wanted configuration of those pins is *not* soc-specific but board-specific. From a fast look, I can see that at least the I2C pins can be assigned to different functions: for example, pins 15+16 can be either of i2c0_1, *or* u30_phy_i2c0, *or* u32_phy_i2c0, *or* xfi_phy0_i2c1 ... or others, even. Finally - I think that *most* of the muxing that you're declaring here must instead go to your board specific devicetree and not in mt7988a.dtsi. Cheers, Angelo