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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c0e55a53fcsm1134929eec.24.2026.03.17.13.25.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Mar 2026 13:25:08 -0700 (PDT) Message-ID: <4afceefe-8053-4c10-8595-39dab9379aab@oss.qualcomm.com> Date: Tue, 17 Mar 2026 13:25:07 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Bryan O'Donoghue , Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260315-x1e-csi2-phy-v4-0-90c09203888d@linaro.org> <20260315-x1e-csi2-phy-v4-1-90c09203888d@linaro.org> <3VqSGUgMUKaCja5WYOrOP8nJ_mw_eDPdItA8d1CvqUg4ASPS5IUc_aT2E-XIo0YmnYo8QltXVw8_6NDxtdqGGw==@protonmail.internalid> <5705b48a-fc24-4c5f-aa6d-40952f0070d9@oss.qualcomm.com> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDE3OSBTYWx0ZWRfX/RcKPUfrBf2J 3RiaXgzEr3nQ76l7igodhG6zrtyq2J/DcswpNl8xvFyjU/Zm4S+ojBCoV2sdWfRyhnwrPREaPIL p89vxvXCg3g+S5Uoh79z+yYmSWRfNgVLZBOL6acrD9M5ygWYqz/khR92qtF5Ci0hTQyp2LtRt66 Wc0QVkaRq4VEgN9DXsgAvL0iBIa33SaEPseYw+rPHSfPJMXUvqbvOh1c6pyoHxqsVILiTK1rbUw XAHisG8TI6DzjC/K5qcardaUu1xptTR91AxLjCzdb6wFHH073ngtxaFA9l9aVmE8oo42U9mA3jI 3OIqBLKcF5DB0qwYG4rFqPDRDF7K8HSQGufc28OsKydYYYx/ItKbx0ow3b7pdHH9wkmnxo4X2bq ijcoQGV27vEzYj7caxGM+vTl35kmidNzPKSaqK2Nbl81r3RZWDOHK7qxkrzgXJp+l3vl6T6qLoF LtDHrVHtiLYopCQjssw== X-Authority-Analysis: v=2.4 cv=P8I3RyAu c=1 sm=1 tr=0 ts=69b9b8a6 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=CIW99FJ8g63gKaA5L-sA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 1_KsR2clIAg_bnfq3cqtO7GZMK-n_h7t X-Proofpoint-GUID: 1_KsR2clIAg_bnfq3cqtO7GZMK-n_h7t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_04,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170179 On 3/16/2026 10:26 PM, Bryan O'Donoghue wrote: > On 16/03/2026 21:31, Vijay Kumar Tumati wrote: >> Hi Bryan, >> >> On 3/15/2026 4:52 PM, Bryan O'Donoghue wrote: >>> Add a base schema initially compatible with x1e80100 to describe MIPI >>> CSI2 >>> PHY devices. >>> >>> The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices >>> have their own pinouts on the SoC as well as their own individual >>> voltage >>> rails. >>> >>> The need to model voltage rails on a per-PHY basis leads us to define >>> CSIPHY devices as individual nodes. >>> >>> Two nice outcomes in terms of schema and DT arise from this change. >>> >>> 1. The ability to define on a per-PHY basis voltage rails. >>> 2. The ability to require those voltage. >>> >>> We have had a complete bodge upstream for this where a single set of >>> voltage rail for all CSIPHYs has been buried inside of CAMSS. >>> >>> Much like the I2C bus which is dedicated to Camera sensors - the CCI >>> bus in >>> CAMSS parlance, the CSIPHY devices should be individually modelled. >>> >>> Signed-off-by: Bryan O'Donoghue >>> --- >>>    .../bindings/phy/qcom,x1e80100-csi2-phy.yaml       | 133 +++++++++ >>> ++++++++++++ >>>    1 file changed, 133 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100- >>> csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100- >>> csi2-phy.yaml >>> new file mode 100644 >>> index 0000000000000..b83c2d65ebc6e >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml >>> @@ -0,0 +1,133 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm CSI2 PHY >>> + >>> +maintainers: >>> +  - Bryan O'Donoghue >>> + >>> +description: >>> +  Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 >>> sensors >>> +  to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and >>> D-PHY >>> +  modes. >>> + >>> +properties: >>> +  compatible: >>> +    const: qcom,x1e80100-csi2-phy >>> + >>> +  reg: >>> +    maxItems: 1 >>> + >>> +  "#phy-cells": >>> +    const: 1 >>> + >>> +  clocks: >>> +    maxItems: 4 >>> + >>> +  clock-names: >>> +    items: >>> +      - const: csiphy >>> +      - const: csiphy_timer >>> +      - const: camnoc_axi >>> +      - const: cpas_ahb >>> + >>> +  interrupts: >>> +    maxItems: 1 >>> + >>> +  operating-points-v2: >>> +    maxItems: 1 >>> + >>> +  power-domains: >>> +    items: >>> +      - description: TITAN TOP GDSC >>> +      - description: MXC or MXA voltage rail >> Would it be better to provision MXA or MXC as an additional optional >> power domain? I see 'cam_cc_cphy_rx_clk_src', the parent of all CSIPHYx >> clocks, need all three power domains on this chipset. > > I don't think this should be optional. Have the dts point to an "mx" > power-domain and then select which one is right for a PHY MX/MXA or MXC. > > Your worst case here is some future PHY which has more or fewer PDs > which is then either a special case in this file or a whole new file for > that compat. > I think it is the case on x1e* as well, Bryan. >>> +      - description: MMCX voltage rail >>> + >>> +  power-domain-names: >>> +    items: >>> +      - const: top >>> +      - const: mx >>> +      - const: mmcx >>> + >>> +  vdda-0p8-supply: >>> +    description: Phandle to a 0.8V regulator supply to a PHY. >>> + >>> +  vdda-1p2-supply: >>> +    description: Phandle to 1.2V regulator supply to a PHY. >>> + >>> +required: >>> +  - compatible >>> +  - reg >>> +  - "#phy-cells" >>> +  - clocks >>> +  - clock-names >>> +  - interrupts >>> +  - operating-points-v2 >>> +  - power-domains >>> +  - power-domain-names >>> +  - vdda-0p8-supply >>> +  - vdda-1p2-supply >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> +  - | >>> +    #include >>> +    #include >>> +    #include >>> +    #include >>> +    #include >>> + >>> +    csiphy@ace4000 { >>> +        compatible = "qcom,x1e80100-csi2-phy"; >>> +        reg = <0x0ace4000 0x2000>; >>> +        #phy-cells = <1>; >>> + >>> +        clocks = <&camcc CAM_CC_CSIPHY0_CLK>, >>> +                 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, >>> +                 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, >>> +                 <&camcc CAM_CC_CPAS_AHB_CLK>; >>> +        clock-names = "csiphy", >>> +                      "csiphy_timer", >>> +                      "camnoc_axi", >>> +                      "cpas_ahb"; >> Although it's not a concern from my side, just want to be explicitly >> sure that everyone is happy with the clock names, just to avoid any >> changes later on when other modules are separated out. > > These are the names we already use in CAMSS so ... they're good enough > to start from. > Sure, FYI: Dmitry, Konrad. >>> + >>> +        operating-points-v2 = <&csiphy_opp_table>; >>> + >>> +        interrupts = ; >>> + >>> +        power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, >>> +                        <&rpmhpd RPMHPD_MX>, >>> +                        <&rpmhpd RPMHPD_MMCX>; >>> +        power-domain-names = "top", >>> +                             "mx", >>> +                             "mmcx"; >>> + >>> +        vdda-0p8-supply = <&vreg_l2c_0p8>; >>> +        vdda-1p2-supply = <&vreg_l1c_1p2>; >>> +    }; >>> + >>> +    csiphy_opp_table: opp-table { >>> +        compatible = "operating-points-v2"; >>> + >>> +        opp-300000000 { >>> +            opp-hz = /bits/ 64 <300000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs_d1>, >>> +                            <&rpmhpd_opp_low_svs_d1>; >>> +        }; >>> + >>> +        opp-400000000 { >>> +            opp-hz = /bits/ 64 <400000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>, >>> +                            <&rpmhpd_opp_low_svs>; >>> +        }; >>> + >>> +        opp-480000000 { >>> +            opp-hz = /bits/ 64 <480000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>, >>> +                            <&rpmhpd_opp_low_svs>; >> 480mhz should be svs? > > Yes you're right thanks for spotting. > >>> +        }; >>> +    }; >>> >> Thanks, >> Vijay. > Thanks, Vijay.