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> + u32 status; > + int ret; > + > + if (!cfg->dp_aux_cfg2) { > + dev_err(qmp->dev, "DP AUX CFG2 value not configured\n"); > + return -EINVAL; > + } > + > + writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); > + > + qmp_combo_configure_dp_mode(qmp); > + > + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); > + writel(cfg->dp_aux_cfg2, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); > + > + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); > + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); > + > + ret = qmp->cfg->configure_dp_clocks(qmp); > + if (ret) > + return ret; > + > + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); > + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); > + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); > + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); > + > + writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); > + > + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], > + status, > + ((status & BIT(0)) > 0), > + 500, > + 10000)) > + return -ETIMEDOUT; > + > + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], > + status, > + ((status & BIT(0)) > 0), > + 500, > + 10000)) > + return -ETIMEDOUT; > + > + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], > + status, > + ((status & BIT(1)) > 0), > + 500, > + 10000)) > + return -ETIMEDOUT; > + > + return 0; > +} > + > static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) > { > const struct qmp_phy_cfg *cfg = qmp->cfg; > > - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | > - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, > - qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); > + writel(0x3f, qmp->dp_serdes + QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1); > + > + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | > + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | > + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, > + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); > > /* Turn on BIAS current for PHY/PLL */ > - writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); > + writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); > > writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); > writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); > @@ -3729,8 +3807,8 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) > writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); > writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); > > - writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); > - writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); > + writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); > + writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); > > qmp_combo_configure_dp_swing(qmp); > } > @@ -3738,48 +3816,41 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) > static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) > { > const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; > - u32 phy_vco_div; > unsigned long pixel_freq; > - const struct qmp_phy_cfg *cfg = qmp->cfg; > > switch (dp_opts->link_rate) { > case 1620: > - phy_vco_div = 0x4; > pixel_freq = 1620000000UL / 2; > break; > case 2700: > - phy_vco_div = 0x2; > pixel_freq = 2700000000UL / 2; > break; > case 5400: > - phy_vco_div = 0x4; > pixel_freq = 5400000000UL / 4; > break; > case 8100: > - phy_vco_div = 0x3; > pixel_freq = 8100000000UL / 6; > break; > default: > /* Other link rates aren't supported */ > return -EINVAL; > } > - writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); > > /* disable core reset tsync */ > writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); > > - writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); > - writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); > + writel(0x09, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); > + writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); > writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); > - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); > + writel(0x33, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); These 3 altered writes depend on the rate > > writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); > writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); > writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); > writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); > - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); > + writel(0x33, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); This is duplicated, it seems > writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); > - writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); > + writel(0x02, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); This depends on swing/preem levels [...] > @@ -3938,13 +3971,13 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) > } else if (dp_opts->lanes == 2) { > bias0_en = reverse ? 0x3f : 0x15; > bias1_en = reverse ? 0x15 : 0x3f; > - drvr0_en = 0x10; > - drvr1_en = 0x10; > + drvr0_en = 0x30; > + drvr1_en = 0x30; > } else { > bias0_en = 0x3f; > bias1_en = 0x3f; > - drvr0_en = 0x34; > - drvr1_en = 0x34; > + drvr0_en = 0x30; > + drvr1_en = 0x30; 2ln settings should also depend on the reverse state > } > > writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); > @@ -3952,6 +3985,15 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) > writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); > writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); > This should also be preceded by LANE_CLKBUF_EN, I think > + writel(0x03, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); > + writel(0x23, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); > + writel(0x22, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); > + > + writel(0x0a, qmp->dp_tx + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); > + writel(0x0a, qmp->dp_tx2 + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); > + > + writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); Konrad