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Thu, 11 Jul 2024 00:32:23 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 11 Jul 2024 00:32:22 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 11 Jul 2024 00:32:22 -0500 Received: from localhost (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46B5WLub101320; Thu, 11 Jul 2024 00:32:22 -0500 Date: Thu, 11 Jul 2024 11:02:21 +0530 From: Siddharth Vadapalli To: Andrew Halaney CC: Nishanth Menon , Vignesh Raghavendra , "Tero Kristo" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Philipp Zabel" , Siddharth Vadapalli , , , , Subject: Re: [PATCH 1/2] arm64: dts: ti: k3-j784s4-evm: Assign only lanes 0 and 1 to PCIe1 Message-ID: <4b13252c-31ed-4122-89e4-3fdae95077e5@ti.com> References: <20240710-k3-j784s4-evm-serdes0-cleanup-v1-0-03850fe33922@redhat.com> <20240710-k3-j784s4-evm-serdes0-cleanup-v1-1-03850fe33922@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240710-k3-j784s4-evm-serdes0-cleanup-v1-1-03850fe33922@redhat.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On Wed, Jul 10, 2024 at 10:36:13AM -0500, Andrew Halaney wrote: > Currently PCIe1 is setup to use SERDES0 lanes 0 thru 3, and USB0 is > setup to use SERDES0 lane 3 as well. > > This overlap in lanes causes the following reset related lane splat: > > [ 4.846266] WARNING: CPU: 4 PID: 308 at drivers/reset/core.c:792 __reset_control_get_internal+0x128/0x160 > ... > [ 4.846405] Call trace: > [ 4.846407] __reset_control_get_internal+0x128/0x160 > [ 4.846413] __of_reset_control_get+0x4e0/0x528 > [ 4.846418] of_reset_control_array_get+0xa4/0x1f8 > [ 4.846423] cdns_torrent_phy_probe+0xbc8/0x1068 [phy_cadence_torrent] > [ 4.846445] platform_probe+0xb4/0xe8 > ... > [ 4.846577] cdns-torrent-phy 5060000.serdes: phy@0: failed to get reset > > Let's limit the PCIe1 SERDES0 lanes to 0 and 1 to avoid overlap here. > This works since PCIe1 operates in x2 mode and doesn't need 4 SERDES0 > lanes. > > Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode") > Suggested-by: Siddharth Vadapalli > Signed-off-by: Andrew Halaney Thank you for posting this patch. Reviewed-by: Siddharth Vadapalli Regards, Siddharth.