Re: [PATCH] x86/fpu: Warn only when CPU-provided sizes less than struct declaration

[Dave Hansen <dave.hansen@intel.com>]

On 12/6/19 12:14 AM, Suravee Suthikulpanit wrote:
> On 12/4/19 12:27 AM, Dave Hansen wrote:
>> On 12/3/19 1:01 AM, Suravee Suthikulpanit wrote:
>>> The current XCHECK_SZ macro warns if the XFEATURE size reported
>>> by CPUID does not match the size of kernel structure. However, depending
>>> on the hardware implementation, CPUID can report the XSAVE state size
>>> larger than the size of C structures defined for each of the XSAVE state
>>> due to padding.
>>
>> We have existing architecture for padding.  See xfeature_is_aligned(),
>> for instance.  Are you saying that there are implementations out there
>> that do padding which is not otherwise enumerated and that they do it
>> within the size of the enumerated stat
> Yes, the implementation includes the padding size within the size of
> the enumerated state. This results in the reported size larger than
> the amount needed by the feature.

I don't think we've ever had XSAVE state that differed in size between
implementations.  This kind of thing ensures that we can't have any
statically-defined inspection into the XSAVE state.

It also increases the amount of blind trust that we have in the CPU
implementations.  However, those warnings were specifically added at
Ingo's behest (IIRC) to reduce our blind trust in the CPU.

>>> Such case should be safe and should not need to generate warning
>>> message.
>>
>> I've seen these error messages trip before, but only on pre-production
>> processors with goofy microcode.  I'd be really suspicious that this is
>> just papering over a processor issue.  Or, that perhaps the compacted
>> form works but the standard form is broken somehow.
> 
> I have verified with the HW folks and the have confirmed that this is
> to be expected.

From a review perspective, I'd really appreciate being able to have a
concrete discussion about exactly which state this is and exactly how
much padding we are talking about and *why* the existing padding
architecture can't be used.  I'd also want guarantees about this state
not getting used for any real state, *ever*.

I'm not sure how we can have those conversations without more details,
though.  Would you be able, for instance, to have a private discussion
with the x86 maintainers?  That discussion could, understandably,
exclude folks from Intel.