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Mon, 23 Feb 2026 12:28:23 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v3 04/10] iommu/arm-smmu-v3: Pass in IOTLB cache tag to arm_smmu_master_build_invs() Date: Mon, 23 Feb 2026 12:27:40 -0800 Message-ID: <4b42c150b92d0e16566dea661fcb6810f89170d1.1771877893.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E65:EE_|CY5PR12MB6060:EE_ X-MS-Office365-Filtering-Correlation-Id: 994f3096-b540-47a3-db0f-08de731a23df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?A4W/myA1owSxf3fgULNI/AROur0sqOrTxjSAyQysJ/FQM3ct7wjdx9S6LG+0?= =?us-ascii?Q?QM8+aa6OnDw975uSz8edywwH+Zl44rJyNSXkDlQ+iVGSF/Wsjr5CLvwVC0F6?= =?us-ascii?Q?15ziR+5NebS2pzd7nzySN63M/uX7WZcOgHLNH6AVkjGWt9Xm5kuoIShQ8Npc?= =?us-ascii?Q?xvJWbuiNAQDEyHWd0aDBRHgRg0D4ZovXDULoa3L/TlTA5LEJQsF2rrWKYgdh?= =?us-ascii?Q?iSBvRSbOJ1TBZ7e+Dw8GQLhjmhPJyL+aIv2LD1Jaj8Dr+oPC7DwBcDOncW6u?= =?us-ascii?Q?1gBU/A2SeWRsv58nEu8nQVs3qMWw+s/KPROSUsqeDMeYVz8ZcE1iOTw4LULS?= =?us-ascii?Q?RGftZsK0eae7eLxiw+spDYq3fNCVxcJWiXISd7I5SCJFSf6B/kd5gFOb+UAA?= =?us-ascii?Q?/EiLm6OZTQvA4jZ7pEr3uqoRlAJtM/WIABcLGiCo/Cd/H51BLFzlDewOJYWD?= =?us-ascii?Q?9wq1DUUEXdyh/0BiQKMXoOQkGzUVa4KMeQsz+XGELtXxsoSTXy/thQhcC+o2?= =?us-ascii?Q?EUkd/a86giRgGL6Bved3qYmFkikxKiHLTeF0VU43V6B1Y+EqclOx1bWXcZQe?= =?us-ascii?Q?T9uL6tfLMXuycLMZV1qgjSYCW/+0ZmCOL4GTJReqRwrxRp/JplC9fw9aLnuw?= =?us-ascii?Q?pB0BcGauiAQQGZrF4oOdyvecP4/Hq0bTJ9uKyvvARX2aavEP3wd1fkIqA/sO?= =?us-ascii?Q?D7a/OLXRyuMTIP7w+tGI9qS7OON0nLtLqwJ174Zw5gva8oLTWSET1u4HOL9R?= =?us-ascii?Q?/Oe3ls4p35EQRhHTFth7PHpah6yzf7VfekyXvJhNh5fUFW2yAJmM7lB6ZB4b?= =?us-ascii?Q?PwK9GU/JRdAA3L7tvsW2dPqRYSBjUS4oIhedhsMKTS25Rpo7SDmq6N5D6Kj4?= =?us-ascii?Q?KVDfoL12+lbqPVy/AL0ZZPfPJcIRTeOEyYdU6zc+FYNv1IvgmoWzaafuy+pm?= =?us-ascii?Q?pfUdQT3m78wylQGTeBBb7FObtsKQ7teH1IK0+72u7PZ9SHC3n8WP27xGxgBv?= =?us-ascii?Q?gfA/qLlP/TxNs8DjF+CFCqqecZJ3OM44n2UPzveLXAt6wO+6Y7ya7FiQzUM8?= =?us-ascii?Q?yMFC+TQZaaZBuruXaIKB7Z1M/vdnzzZd7VeFWPMOLQOGIg2WpW2HOIh+hbzJ?= =?us-ascii?Q?XuAGEh/cJOtMw73rP75nSj9kJRU9agbZCwRXajzklvU3QlX6NRE+vVRMraPN?= =?us-ascii?Q?lglERb0m5Uqj0aG9KNjVcqpvztsBkJeNm0ubiyzlzrOgNbE9qXVl9tXeJScV?= =?us-ascii?Q?Zgw48ztozcOBzBtH1jac/ir202nRCgqFBQUBWnDGEsFW8nLF5yGQURZol4qV?= =?us-ascii?Q?l5uy4ULFT8J1WrkWI4Psd46AC6+Zr8R0iAlQtL86Lr2+f0ypnxh7krjro9Be?= =?us-ascii?Q?VZ2yzSUL7bYijZgSrPYb+7vMG02FE8SknTNj265ljwXfk8mtO0pFMwz7+lmD?= =?us-ascii?Q?cFrCe7ODWpZYRT354f3wPhnX9z8KMnBGwFgIf8W9wRN7hRPd0y8nN/d0ELmp?= =?us-ascii?Q?I7Xhb128T+MSNIsgO2ZqaT9pa2wVtQQLUrKsOg8vDQAWMubFCmPVvqnKAvkc?= =?us-ascii?Q?WpxPO5oC+6Dsj5bj+c7vziIyT1/WXpO16Bi2iJR39fEubCLtQxHsQD2fc/zu?= =?us-ascii?Q?ARXiPncTDbdJwCcj2pKxTOWx69KJFya8E0q3TJnHWXnE?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UgQ3NqxY6imhGxY754ZfDzl9jiFGc3F/mD8pD1lU+s1afMQjFHvPARU3QWEdHAJ/Y/vqZOJjJjzzcsxE71WC3AOBaffvVz1g+Y/hlfC9jylD3ZrEGYkfKbzJnVW8AAEDD5Fxys1QAGtOr2gQSJ7btoUZQs9/gpGarWyJ8pBgY0/OEzQkBdqxK5Tql6DRecQc90qvHOKjFoGKDNMDzaWsAKjOpjOH7iaNlRG0pR+B1G+3/WC9qSKUx8CJXLB9oUmhLMuodaYZBNbPzMLMczXB/lMNJe302Qi6c/GtarZ+alC0A/gXax4IP01SniBtl0ZOoHt2jBTJiPH3D+CHn6VjZBk5EDu++BE8wXZvbdmBI7fhHd5q3a/T+zhHdMEjPEjAbULG9SGb26i51n7mKTkcCGkbj7t6jjdGP6feXdPlaSKNNq0lv7KB1w/QTXWjlsrq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:28:44.0917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 994f3096-b540-47a3-db0f-08de731a23df X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E65.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6060 Now struct arm_smmu_attach_state carrys an IOTLB cache tag in invst->tag. Instead of getting the tag from smmu_domain again, pass in the invst->tag to arm_smmu_master_build_invs(). This could simplify the function. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 37 ++++++++------------- 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 2033468dbf1e8..4649368910e0c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3330,7 +3330,8 @@ arm_smmu_master_build_inv(struct arm_smmu_master *master, */ static struct arm_smmu_invs * arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enabled, - ioasid_t ssid, struct arm_smmu_domain *smmu_domain) + ioasid_t ssid, struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag) { const bool nesting = smmu_domain->nest_parent; size_t pgsize = 0, i; @@ -3343,30 +3344,15 @@ arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enabled, if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) pgsize = __ffs(smmu_domain->domain.pgsize_bitmap); - switch (smmu_domain->stage) { - case ARM_SMMU_DOMAIN_SVA: - case ARM_SMMU_DOMAIN_S1: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, - smmu_domain->cd.asid, - IOMMU_NO_PASID, pgsize)) - return NULL; - break; - case ARM_SMMU_DOMAIN_S2: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, - smmu_domain->s2_cfg.vmid, - IOMMU_NO_PASID, pgsize)) - return NULL; - break; - default: - WARN_ON(true); + if (!arm_smmu_master_build_inv(master, tag->type, tag->id, + IOMMU_NO_PASID, pgsize)) return NULL; - } /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ if (nesting) { - if (!arm_smmu_master_build_inv( - master, INV_TYPE_S2_VMID_S1_CLEAR, - smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + if (!arm_smmu_master_build_inv(master, + INV_TYPE_S2_VMID_S1_CLEAR, + tag->id, IOMMU_NO_PASID, 0)) return NULL; } @@ -3457,8 +3443,10 @@ static int arm_smmu_attach_prepare_invs(struct arm_smmu_attach_state *state, if (ret) return ret; - build_invs = arm_smmu_master_build_invs( - master, state->ats_enabled, ssid, new_smmu_domain); + build_invs = arm_smmu_master_build_invs(master, + state->ats_enabled, + ssid, new_smmu_domain, + &invst->tag); if (!build_invs) return -EINVAL; @@ -3487,7 +3475,8 @@ static int arm_smmu_attach_prepare_invs(struct arm_smmu_attach_state *state, /* For old_smmu_domain, new_invs points to master->build_invs */ invst->new_invs = arm_smmu_master_build_invs( - master, master->ats_enabled, ssid, old_smmu_domain); + master, master->ats_enabled, ssid, old_smmu_domain, + &invst->tag); } return 0; -- 2.43.0