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Fri, 14 Feb 2025 01:34:42 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51E1YgIW030624 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Feb 2025 01:34:42 GMT Received: from [10.133.33.20] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Feb 2025 17:34:37 -0800 Message-ID: <4b521b49-7104-4f25-82cb-4f9be7b235f4@quicinc.com> Date: Fri, 14 Feb 2025 09:34:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/7] Coresight: Introduce a new struct coresight_path To: James Clark CC: Tingwei Zhang , Jinlong Mao , , , , , , , Suzuki K Poulose , Mike Leach , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> <20250207064213.2314482-5-quic_jiegan@quicinc.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: n12lx9MUXtTmuN9oW17JdwUUnfTKoQSB X-Proofpoint-ORIG-GUID: n12lx9MUXtTmuN9oW17JdwUUnfTKoQSB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_09,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=792 priorityscore=1501 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502140008 On 2/14/2025 12:00 AM, James Clark wrote: > > > On 07/02/2025 6:42 am, Jie Gan wrote: >> Add 'struct coresight_path' to store the data that is needed by >> coresight_enable_path/coresight_disable_path. The structure will be >> transmitted to any required devices to enable related funcationalities. >> >> The trace_id will be allocated after the path is built. Consequently, >> The ETM3x and ETM4x devices will directly read the trace_id from path >> which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id >> being deleted. >> >> Co-developed-by: James Clark >> Signed-off-by: James Clark >> Signed-off-by: Jie Gan >> --- >>   drivers/hwtracing/coresight/coresight-core.c  | 106 +++++++++++++----- >>   drivers/hwtracing/coresight/coresight-dummy.c |   5 +- >>   .../hwtracing/coresight/coresight-etm-perf.c  |  30 +++-- >>   .../hwtracing/coresight/coresight-etm-perf.h  |   2 +- >>   drivers/hwtracing/coresight/coresight-etm.h   |   1 - >>   .../coresight/coresight-etm3x-core.c          |  54 ++------- >>   .../coresight/coresight-etm4x-core.c          |  54 ++------- >>   drivers/hwtracing/coresight/coresight-etm4x.h |   1 - >>   drivers/hwtracing/coresight/coresight-priv.h  |  12 +- >>   drivers/hwtracing/coresight/coresight-stm.c   |   3 +- >>   drivers/hwtracing/coresight/coresight-sysfs.c |  17 ++- >>   drivers/hwtracing/coresight/coresight-tpdm.c  |   3 +- >>   include/linux/coresight.h                     |  12 +- >>   13 files changed, 143 insertions(+), 157 deletions(-) >> > [...] >> @@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event >> *event, void **pages, >>        * CPUs, we can handle it and fail the session. >>        */ >>       for_each_cpu(cpu, mask) { >> -        struct list_head *path; >> +        struct coresight_path *path; >>           struct coresight_device *csdev; >>           csdev = per_cpu(csdev_src, cpu); >> @@ -405,15 +405,15 @@ static void *etm_setup_aux(struct perf_event >> *event, void **pages, >>               cpumask_clear_cpu(cpu, mask); >>               continue; >>           } >> - >>           /* ensure we can allocate a trace ID for this CPU */ >> -        trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink- >> >perf_sink_id_map); >> -        if (!IS_VALID_CS_TRACE_ID(trace_id)) { >> +        trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF); >> + >> +        /* Can be 0 and valid, ETE doesn't need an ID */ >> +        if (trace_id < 0) { > > Not sure why I wrote it like this, but I think we should leave it as it > was with !IS_VALID_CS_TRACE_ID(). Even with ETE it calls the trace ID > allocator, so nothing has changed here. > Sure, Will restore. For ETE or ETM, we dont need traverse the path, just directly allocate the trace id based on cpu id. Jie