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Fri, 6 Feb 2026 08:19:00 -0600 Message-ID: <4b554339-95e1-4980-8899-57ba637ba80c@ti.com> Date: Fri, 6 Feb 2026 19:48:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , References: <20260129150601.185882-1-s-jain1@ti.com> <20260205-spectral-dramatic-jellyfish-cec4e2@quoll> Content-Language: en-US From: Swamil Jain In-Reply-To: <20260205-spectral-dramatic-jellyfish-cec4e2@quoll> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4C:EE_|SJ5PPF842B33876:EE_ X-MS-Office365-Filtering-Correlation-Id: e274ad3f-2f96-45ed-bff9-08de658ab385 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 05tuhDgwLNy+O56NtpXvnt+h7e0gAgL339tm9tyrbfYSrKu/ZOcmQiB+hR+dRP+MOLUmk+Yb7wRkWYZgnlxX4VkjO12dL2ObWCFG6y++qhlnspgObmWESAhpZQYQAtTRpVdnBzlrf8w+ZSD4NKLUJtpNC0II6+CAYtGxqH+zv+/oBVpe5+brNCIMgqbmaz6604IfYN/AN73IZndgoYQWyMCNJRlDrGfKDFNB+FP7ZiY67GrXVyjDYzeJEJosPacqqmPXP0nWztfrT+34au4O+1EWwVeLWfsRr9YdnuKF5BlgFT6qL458isyu/3iA08C1omIXL1bPB6i64E4K8GLf0W08694VqPrPlX8KHXsj3Y2vy6uWF1tWRRS4PtFoY38Rk7jrS+pw/vzJ4RmWtk+77hYMNa6B94p7Lk57O43Kfe6ndRyU5E4ptzZPPNerk3xN X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2026 14:19:12.4287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e274ad3f-2f96-45ed-bff9-08de658ab385 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF842B33876 Hi Krzysztof, On 2/5/26 18:55, Krzysztof Kozlowski wrote: > On Thu, Jan 29, 2026 at 08:36:01PM +0530, Swamil Jain wrote: >> The AM62L DSS [1] support incorrectly used the same register and >> clock constraints as AM65x, but AM62L has a single video port. >> >> Fix this by adding conditional constraints that properly define the >> register regions and clocks for AM62L DSS (single video port) versus >> other AM65x variants (dual video port). >> >> [1]: Section 12.7 (Display Subsystem and Peripherals) >> Link : https://www.ti.com/lit/pdf/sprujb4 >> >> Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS") >> Cc: stable@vger.kernel.org >> > > There are never blank lines between tags. > Sorry, will fix this. >> Signed-off-by: Swamil Jain >> --- >> Changelog: >> v1->v2: >> - Remove oneOf from top level constraints, it makes bindings redundant >> - Remove minItems from top level constraints >> - "dma-coherent" property shouldn't be changed in v1 itself >> - Add description for reg-names, clock and clock-names >> - Add constraints specific to AM62L and for other SoCs within allOf >> check >> >> Link to v1: >> https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/ >> --- >> .../bindings/display/ti/ti,am65x-dss.yaml | 93 +++++++++++++------ >> 1 file changed, 67 insertions(+), 26 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index 38fcee91211e..dbc9d754cf9e 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -36,38 +36,18 @@ properties: >> reg: >> description: >> Addresses to each DSS memory region described in the SoC's TRM. >> - items: >> - - description: common DSS register area >> - - description: VIDL1 light video plane >> - - description: VID video plane >> - - description: OVR1 overlay manager for vp1 >> - - description: OVR2 overlay manager for vp2 >> - - description: VP1 video port 1 >> - - description: VP2 video port 2 >> - - description: common1 DSS register area > > No, I do not understand this change. We spoke so many times, documented > it, wrotre on presentation slides: broadest constraints are always > defined in top level. TI received this feedback more than once. > There is no superset constraints since am62l register sequence (common, vidl1, ovr1, vp1, common1) is different than non-am62l SoCs (common, vidl1, vid, ...-> here it is different), so thought to adopt this approach where there is if-else block for each SoC and ran this through dt-bindings check as well, looking at the replies maybe I misunderstood what the suggestion was, reading the reply as I understand below is the suggestion: ``` reg: description: Addresses to each DSS memory region described in the SoC's TRM. oneOf: - items: - description: common DSS register area - description: VIDL1 light video plane - description: VID video plane - description: OVR1 overlay manager for vp1 - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 - description: common1 DSS register area - items: - description: common DSS register area - description: VIDL1 light video plane - description: OVR1 overlay manager for vp1 - description: VP1 video port 1 - description: common1 DSS register area .....(Similarly for reg-names, clocks, clock-names,...) allOf: - if: properties: compatible: contains: const: ti,am62l-dss then: properties: clock-names: maxItems: 2 clocks: maxItems: 2 reg: maxItems: 5 else: properties: clock-names: minItems: 3 clocks: minItems: 3 reg: minItems: 8 ``` Could you please confirm on this? Regards, Swamil. > Sorry guys, but you are not individual contributors which do it in spare > time. Why the same feedback - already documented - has to be repeated? > > Best regards, > Krzysztof > >