From: "Clément Léger" <cleger@rivosinc.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: hwprobe: export Zabha extension
Date: Tue, 22 Apr 2025 14:26:39 +0200 [thread overview]
Message-ID: <4b950430-6f12-4b4d-a516-e09a38b83ff0@rivosinc.com> (raw)
In-Reply-To: <20250421141413.394444-1-alexghiti@rivosinc.com>
On 21/04/2025 16:14, Alexandre Ghiti wrote:
> Export Zabha through the hwprobe syscall.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index f60bf5991755..a4998ad2dfe0 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -271,6 +271,10 @@ The following keys are defined:
> * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
> ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as
> + ratified in commit 49f49c842ff9 ("Update to Rafified state") of
> + riscv-zabha.
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
> :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
> mistakenly classified as a bitmask rather than a value.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 3c2fce939673..fca15f2bf6f3 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -81,6 +81,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
> #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
> #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
> +#define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 249aec8594a9..ed3123396a96 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -96,6 +96,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> * presence in the hart_isa bitmap, are made.
> */
> EXT_KEY(ZAAMO);
> + EXT_KEY(ZABHA);
> EXT_KEY(ZACAS);
> EXT_KEY(ZALRSC);
> EXT_KEY(ZAWRS);
Hi Alex,
Looks good to me,
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Thanks,
Clément
next prev parent reply other threads:[~2025-04-22 12:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-21 14:14 Alexandre Ghiti
2025-04-22 12:26 ` Clément Léger [this message]
2025-06-02 22:12 ` patchwork-bot+linux-riscv
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