From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756479AbdGYBFf (ORCPT ); Mon, 24 Jul 2017 21:05:35 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:43890 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755981AbdGYBF2 (ORCPT ); Mon, 24 Jul 2017 21:05:28 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1DBDF607C8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=fenglinw@codeaurora.org Subject: Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Add support for qcom,gpios-disallowed property To: Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, Linus Walleij , Mark Rutland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, collinsd@codeaurora.org, aghayal@codeaurora.org, wruan@codeaurora.org, kgunda@codeaurora.org References: <20170719071804.3816-1-fenglinw@codeaurora.org> <20170724190949.y45cx4zextmvb4tn@rob-hp-laptop> From: Fenglin Wu Message-ID: <4bb5757c-44b0-c760-2d70-df0e607de0d7@codeaurora.org> Date: Tue, 25 Jul 2017 09:05:22 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170724190949.y45cx4zextmvb4tn@rob-hp-laptop> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/25/2017 3:09 AM, Rob Herring wrote: >> >> + Definition: Array of the GPIO hardware numbers corresponding to GPIOs >> + which the APSS processor is not allowed to configure. >> + The hardware numbers are indexed from 1. >> + The interrupt resources for these GPIOs must not be defined >> + in "interrupts" and "interrupt-names" properties. >> + GPIOs defined in this array won't be registered as pins >> + in the pinctrl device or gpios in the gpio chip. > Isn't simply not assigning GPIOs to anything in the DT sufficient to not Thanks for the question, Ron. Previous implementation assumes all GPIOs are accessible from APSS processor and it gets the total pin numbers by counting IRQs. It registers pinctrl devices with the total pin numbers and assumes all the pin are indexed continuously from hardware. Current case is, some GPIOs' interrupt are not owned by APSS processor and there would be errors when creating IRQ mapping for them. Yes, We can exclude them from the "interrupts" property but the driver won't shift the GPIO pad index automatically. Such as: PMI8998 has 14 GPIOs from GPIO1 to GPIO14, and GPIO4/GPIO7/GPIO13 are not accessible from APPS processor, we can excluded them from the interrupt assignment (in following sample) and DON'T expect to register pins for them, but the driver would count the IRQ numbers to 11 and register pins for GPIO1 ~ GPIO11. So I am adding this property "qcom,gpios-disallowed" for these inaccessible GPIOs then the driver would exclude them and register pins for the right GPIO pads. Samples: interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>, <0x2 0xc1 0 IRQ_TYPE_NONE>, <0x2 0xc2 0 IRQ_TYPE_NONE>, <0x2 0xc4 0 IRQ_TYPE_NONE>, <0x2 0xc5 0 IRQ_TYPE_NONE>, <0x2 0xc7 0 IRQ_TYPE_NONE>, <0x2 0xc8 0 IRQ_TYPE_NONE>, <0x2 0xc9 0 IRQ_TYPE_NONE>, <0x2 0xca 0 IRQ_TYPE_NONE>, <0x2 0xcb 0 IRQ_TYPE_NONE>, <0x2 0xcd 0 IRQ_TYPE_NONE>; interrupt-names = "pmi8998_gpio1", "pmi8998_gpio2", "pmi8998_gpio3", "pmi8998_gpio5", "pmi8998_gpio6", "pmi8998_gpio8", "pmi8998_gpio9", "pmi8998_gpio10", "pmi8998_gpio11", "pmi8998_gpio12", "pmi8998_gpio14"; qcom,gpios-disallowed = <4 7 13>; -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.