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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id u5sm15851512qka.106.2020.12.14.14.14.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Dec 2020 14:14:58 -0800 (PST) Subject: Re: [PATCH v2 2/2] Documentation: fpga: dfl: Add description for DFL UIO support To: Xu Yilun , mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: gregkh@linuxfoundation.org, lgoncalv@redhat.com, hao.wu@intel.com References: <1607916981-14782-1-git-send-email-yilun.xu@intel.com> <1607916981-14782-3-git-send-email-yilun.xu@intel.com> From: Tom Rix Message-ID: <4bbaa5ad-b0eb-8ea6-9dc6-c08060450e36@redhat.com> Date: Mon, 14 Dec 2020 14:14:56 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <1607916981-14782-3-git-send-email-yilun.xu@intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/13/20 7:36 PM, Xu Yilun wrote: > This patch adds description for UIO support for dfl devices on DFL > bus. > > Signed-off-by: Xu Yilun > --- > v2: no doc in v1, add it for v2. > --- > Documentation/fpga/dfl.rst | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) Should add your self in the authors list. > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index 0404fe6..a15e81e 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -502,6 +502,29 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > could be a reference. > > > +UIO support for DFL devices > +=========================== > +The FPGA is open for users to be reprogramed with newly developed hardware The purpose of an FPGA is to be reprogrammed with newly developed hardware components.  New hardware can > +components. They could instantiate a new private feature in the DFL, and then > +get a DFL device in their system. In some cases users may need a userspace > +driver for the DFL device: > + > +* Users may need to run some diagnostic test for their hardwares. * Users may prototype the kernel driver in user space. > +* Some hardware is designed for specific purposes and does not fit into one of > + the standard kernel subsystems. > + > +This requires the direct access to the MMIO space and interrupt handling in > +userspace. We implemented a dfl-uio-pdev module which exposes the UIO device The dfl-uio-pdev module exposes > +interfaces. It adds the uio_pdrv_genirq platform device with the resources of > +the DFL device, and let the generic UIO platform device driver provide UIO the DLF device, and lets > +support to userspace. Use FPGA_DFL_UIO_PDEV to enable this feature. > + > +The DFL UIO driver has a special matching algorithem. It will match any DFL > +device which could not be handled by other DFL drivers. In this way, it will > +not impact the functionality of the features which are already supported by the > +system. (not sure if this section is needed) > + > + > Open discussion > =============== > FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration