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Tue, 1 Jul 2025 19:52:20 -0700 (PDT) Message-ID: <4bc1c1fd9aa1e97a04d964fc5601155ade52cd2d.camel@icenowy.me> Subject: Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s From: Icenowy Zheng To: Paul Kocialkowski , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-gpio@vger.kernel.org Cc: Yong Deng , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Maxime Ripard , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Linus Walleij , Icenowy Zheng , Andre Przywara Date: Wed, 02 Jul 2025 10:52:10 +0800 In-Reply-To: <20250701201124.812882-6-paulk@sys-base.io> References: <20250701201124.812882-1-paulk@sys-base.io> <20250701201124.812882-6-paulk@sys-base.io> Organization: Anthon Open-Source Community Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External =E5=9C=A8 2025-07-01=E6=98=9F=E6=9C=9F=E4=BA=8C=E7=9A=84 22:11 +0200=EF=BC= =8CPaul Kocialkowski=E5=86=99=E9=81=93=EF=BC=9A > The DE mixer clock is currently set to run at 150 MHz, while the > Allwinner BSP configures it at 300 MHz and other platforms typically > run at 297 MHz. >=20 > 150 MHz appears to be enough given the restricted graphics > capabilities > of the SoC (with a work area of only 1024x1024). However it typically > causes the DE clock to be parented to the periph0 pll instead of the > video PLL. >=20 > While this should generally not be a concern, it appears (based on > experimentation) that both the DE and TCON clocks need to be parented > to the same PLL for these units to work. While we cannot represent > this > constraint in the clock driver, it appears that the TCON clock will > often get parented to the video pll (typically running at 297 MHz for Ah I think pixel clocks are arbitary and nothing could be predicted about it... > the CSI units needs), for instance when driving displays with a 33 > MHz > pixel clock (33 being a natural divider of 297). >=20 > Running the DE clock at 297 MHz will typically result in parenting to > the video pll instead of the periph0 pll, thus making the display > output functional. >=20 > This is all a bit fragile but it solves the issue with displays > running > at 33 Mhz and brings V3s to use the same frequency as other > platforms, > making support more unified. >=20 > Also align and sort the fields of the v3s mixer config while at it. >=20 > Signed-off-by: Paul Kocialkowski > --- > =C2=A0drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++------ > =C2=A01 file changed, 6 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c > b/drivers/gpu/drm/sun4i/sun8i_mixer.c > index 8b41d33baa30..35fdc2451060 100644 > --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c > +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c > @@ -670,12 +670,12 @@ static const struct sun8i_mixer_cfg > sun8i_r40_mixer1_cfg =3D { > =C2=A0}; > =C2=A0 > =C2=A0static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg =3D { > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.vi_num =3D 2, > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.ui_num =3D 1, > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.scaler_mask =3D 0x3, > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.scanline_yuv =3D 2048, > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.ccsc =3D CCSC_MIXER0_LAYOUT, > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.mod_rate =3D 150000000, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.ccsc=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=3D CCSC_MIXER0_LAYOUT, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.mod_rate=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=3D 297000000, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.scaler_mask=C2=A0=C2=A0=C2=A0= =C2=A0=3D 0x3, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.scanline_yuv=C2=A0=C2=A0=C2= =A0=3D 2048, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.ui_num=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=3D 1, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0.vi_num=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=3D 2, > =C2=A0}; > =C2=A0 > =C2=A0static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg =3D {