From: Nabige Aala <nabige.aala@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Wesley Cheng <wesley.cheng@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>,
Johan Hovold <johan+linaro@kernel.org>,
Bjorn Andersson <quic_bjorande@quicinc.com>,
Dmitry Baryshkov <lumag@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>,
Mahadevan P <mahadevan.p@oss.qualcomm.com>
Subject: Re: [PATCH v5 04/11] phy: qualcomm: qmp-combo: Ignore Type-C orientation for Glymur DP mode
Date: Thu, 1 Oct 2026 18:44:48 +0530 [thread overview]
Message-ID: <4bd4199e-8552-4686-ad85-9c3e27b1f967@oss.qualcomm.com> (raw)
In-Reply-To: <rp53rdt4rseek4cjmyqhmwg6rm25nnm7e3p2qvmjkr3l42ymmo@25os6fta5wm3>
On 10/1/2026 3:31 PM, Dmitry Baryshkov wrote:
> On Thu, Oct 01, 2026 at 03:04:21PM +0530, Nabige Aala wrote:
>> From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
>>
>> Glymur platforms use a fixed DP lane mapping and do not support DP PHY
>> mode reversal based on Type-C orientation. Add a configuration flag to
> Does it handle orientation somewhere else? Where? Is it a property of
> the SoC or is it a way how it is plumbed on a particular device?
Hi Dmitry,
This is the Soc-specific property. As defined in glymur HPG DP_PHY_MODE
should always be 0x5c
for all the case 1lane/2lane/4lane and for all the orientation
(normal/flip).
>
>> ignore reverse orientation during DP mode setup and enable it for Glymur,
>> ensuring that QSERDES_DP_PHY_MODE is always programmed with the
>> fix mode value (0x5c).
>>
>> Fixes: 815891eee6687 ("phy: qcom-qmp-combo: Introduce orientation variable")
>> Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
>> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
>> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
next prev parent reply other threads:[~2026-10-01 13:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 9:34 [PATCH v5 00/11] phy: qualcomm: qmp-combo: update DP PHY PLL programming on Glymur Nabige Aala
2026-10-01 9:34 ` [PATCH v5 01/11] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout Nabige Aala
2026-10-01 9:34 ` [PATCH v5 02/11] phy: qualcomm: qmp-combo: Update DP PHY common init tables Nabige Aala
2026-10-01 9:34 ` [PATCH v5 03/11] phy: qualcomm: qmp-combo: Update link rate specific DP PHY tables Nabige Aala
2026-10-01 9:34 ` [PATCH v5 04/11] phy: qualcomm: qmp-combo: Ignore Type-C orientation for Glymur DP mode Nabige Aala
2026-10-01 10:01 ` Dmitry Baryshkov
2026-10-01 13:14 ` Nabige Aala [this message]
2026-10-01 9:34 ` [PATCH v5 05/11] phy: qualcomm: qmp-combo: Add hardware-specific dp_aux_cfg2 and dp_phy_cfg1 fields Nabige Aala
2026-10-01 9:34 ` [PATCH v5 06/11] phy: qualcomm: qmp-combo: Add v8 PCS-level drive level tables for Glymur Nabige Aala
2026-10-01 9:34 ` [PATCH v5 07/11] phy: qualcomm: qmp-combo: Extract common DP PHY init sequence Nabige Aala
2026-10-01 9:34 ` [PATCH v5 08/11] phy: qualcomm: qmp-combo: Remove VCO_DIV programming from qmp_v8_configure_dp_clocks() Nabige Aala
2026-10-01 9:34 ` [PATCH v5 09/11] phy: qualcomm: qmp-combo: Add per-link-rate auxless/LFPS and drive level for Glymur Nabige Aala
2026-10-01 9:34 ` [PATCH v5 10/11] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences Nabige Aala
2026-10-01 9:34 ` [PATCH v5 11/11] phy: qualcomm: qmp-combo: Fix error propagation in qmp_combo_dp_power_on() Nabige Aala
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