From: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Subject: Re: [PATCH] arm64: dts: qcom: nord: Add LLCC node
Date: Wed, 23 Sep 2026 14:38:12 +0530 [thread overview]
Message-ID: <4bd5d1ad-3d97-4ef9-bd46-790bcffd5ea7@oss.qualcomm.com> (raw)
In-Reply-To: <20260922091735.491481-1-shengchao.guo@oss.qualcomm.com>
On 9/22/2026 2:47 PM, Shawn Guo wrote:
> From: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>
> Add the system cache controller. All sixteen banks are listed, four per
> DDR slice at 0x100000 strides from slice + 0x800000, followed by the
> global broadcast OR/AND regions, which the driver expects at the reg
> indices right after the last bank.
>
> No ECC interrupt is described, as the Nord interrupt map does not expose
> one for the LLCC. The driver treats it as optional.
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
> Dependencies:
> - LLCC driver: https://lore.kernel.org/all/20260910-nord_llcc-v1-0-30fd1cca65fe@oss.qualcomm.com/
>
> arch/arm64/boot/dts/qcom/nord.dtsi | 40 ++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c30..6896bda14ef3 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -2071,6 +2071,46 @@ watchdog@17826000 {
> clocks = <&sleep_clk>;
> interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
> };
> +
> + llcc: system-cache-controller@21800000 {
> + compatible = "qcom,nord-llcc";
> + reg = <0x0 0x21800000 0x0 0x100000>,
> + <0x0 0x21a00000 0x0 0x100000>,
> + <0x0 0x21c00000 0x0 0x100000>,
> + <0x0 0x21e00000 0x0 0x100000>,
> + <0x0 0x22800000 0x0 0x100000>,
> + <0x0 0x22a00000 0x0 0x100000>,
> + <0x0 0x22c00000 0x0 0x100000>,
> + <0x0 0x22e00000 0x0 0x100000>,
> + <0x0 0x23800000 0x0 0x100000>,
> + <0x0 0x23a00000 0x0 0x100000>,
> + <0x0 0x23c00000 0x0 0x100000>,
> + <0x0 0x23e00000 0x0 0x100000>,
> + <0x0 0x24800000 0x0 0x100000>,
> + <0x0 0x24a00000 0x0 0x100000>,
> + <0x0 0x24c00000 0x0 0x100000>,
> + <0x0 0x24e00000 0x0 0x100000>,
> + <0x0 0x20400000 0x0 0x100000>,
> + <0x0 0x20600000 0x0 0x100000>;
> + reg-names = "llcc0_base",
> + "llcc1_base",
> + "llcc2_base",
> + "llcc3_base",
> + "llcc4_base",
> + "llcc5_base",
> + "llcc6_base",
> + "llcc7_base",
> + "llcc8_base",
> + "llcc9_base",
> + "llcc10_base",
> + "llcc11_base",
> + "llcc12_base",
> + "llcc13_base",
> + "llcc14_base",
> + "llcc15_base",
> + "llcc_broadcast_base",
> + "llcc_broadcast_and_base";
> + };
> };
>
> arch_timer: timer {
Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
next prev parent reply other threads:[~2026-09-23 9:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 9:17 Shawn Guo
2026-09-23 7:08 ` Bartosz Golaszewski
2026-09-23 9:08 ` Pankaj Patil [this message]
2026-09-24 11:28 ` Abel Vesa
2026-09-25 12:14 ` Konrad Dybcio
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